Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.22 BCTRL1—Bridge Control (D1:F0)
PCI Device: 1
Address Offset: 3Eh
Default Value: 0000h
Access: RO, R/W
Size: 16 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-to-PCI
bridges. The BCTRL provides additional control for the secondary interface (i.e., PCI Express) as
well as some bits that affect the overall behavior of the “virtual” Host-to-PCI Express bridge in
the (G)MCH (e.g., VGA compatible address ranges mapping).
Bit Access &
Default
15:12 Reserved
11 RO
0b
10 RO
0b
9 RO
0b
8 RO
0b
7 RO
0b
6 R/W
0b
5 RO
0b
4 R/W
0b
3 R/W
0b
Description
Discard Timer SERR Enable: Hardwired to 0. Not Applicable or Implemented.
Discard Timer Status: Hardwired to 0. Not Applicable or Implemented.
Secondary Discard Timer: Hardwired to 0. Not Applicable or Implemented.
Primary Discard Timer: Hardwired to 0. Not Applicable or Implemented.
Fast Back-to-Back Enable (FB2BEN): Hardwired to 0. Not Applicable or
Implemented.
Secondary Bus Reset (SRESET):
0 = Hot reset not triggered on the corresponding PCI Express port.
1 = Setting this bit triggers a hot reset on the corresponding PCI Express port.
Master Abort Mode (MAMODE): Hardwired to 0. When acting as a master,
unclaimed reads that experience a master abort return all 1s and any writes that
experience a master abort complete normally and the data is discarded.
VGA 16-bit Decode: This bit enables the PCI-to-PCI bridge to provide 16-bit
decoding of VGA I/O address precluding the decoding of alias addresses every
1 KB. This bit only has meaning if bit 3 (VGA Enable) of this register is also set to
1, enabling VGA I/O decoding and forwarding by the bridge.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
VGA Enable (VGAEN): This bit controls the routing of processor-initiated
transactions targeting VGA compatible I/O and memory address ranges. See the
VGAEN/MDAP table in the LAC Register[0] (Device 0, offset 97h).
126 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet