Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only) 5.1.18 PMLIMIT1—Prefetchable Memory Limit Address (D1:F0) PCI Device: 1 Address Offset: 26h Default Value: 0000h Access: RO, R/W Size: 16 bits This register, in conjunction with the corresponding Upper Limit Address register, controls the processor-to-PCI Express prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE � address � PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40bit address. The lower 8 bits of the Upper Limit Address register are read/write and correspond to address bits A[39:32] of the 40-bit address. The configuration software must initialize this register. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB aligned memory block. Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e., prefetchable) from the processor perspective. Bit Access & Default 15:4 R/W 000h 3:0 RO 0h Description Prefetchable Memory Address Limit (PMLIMIT): This field corresponds to A[31:20] of the upper limit of the address range passed to PCI Express. 64-bit Address Support: This field indicates the bridge only supports 32-bit addresses. 5.1.19 CAPPTR1—Capabilities Pointer (D1:F0) PCI Device: 1 Address Offset: 34h Default Value: 88h Access: RO Size: 8 bits The capabilities pointer provides the address offset to the location of the first entry in this device’s linked list of capabilities. Bit Access & Default 7:0 RO 88h Description First Capability (CAPPTR1): The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability. 124 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
5.1.20 INTRLINE1—Interrupt Line (D1:F0) PCI Device: 1 Address Offset: 3Ch Default Value: 00h Access: R/W Size: 8 bits Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only) This register contains interrupt line routing information. The device itself does not use this value; rather, device drivers and operating systems use it to determine priority and vector information. Bit Access & Default 7:0 R/W 00h 5.1.21 INTRPIN1—Interrupt Pin (D1:F0) PCI Device: 1 Address Offset: 3Dh Default Value: 01h Access: RO Size: 8 bits Description Interrupt Connection: This field is used to communicate interrupt line routing information. POST software writes the routing information into this register as it initializes and configures the system. The value in this register indicates which input of the system interrupt controller is connected to this device’s interrupt pin. This register specifies which interrupt pin this device uses. Bit Access & Default 7:0 RO 01h Description Interrupt Pin: As a single function device, the PCI Express device specifies INTA as its interrupt pin. 01h=INTA. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 125
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5.1.20 INTRLINE1—Interrupt Line (D1:F0)<br />
PCI Device: 1<br />
Address Offset: 3Ch<br />
Default Value: 00h<br />
Access: R/W<br />
Size: 8 bits<br />
Host-PCI <strong>Express</strong>* Bridge Registers (D1:F0) (<strong>Intel®</strong> 82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945P</strong>/82<strong>945P</strong>L Only)<br />
This register contains interrupt line routing information. The device itself does not use this value;<br />
rather, device drivers and operating systems use it to determine priority and vector information.<br />
Bit Access &<br />
Default<br />
7:0 R/W<br />
00h<br />
5.1.21 INTRPIN1—Interrupt Pin (D1:F0)<br />
PCI Device: 1<br />
Address Offset: 3Dh<br />
Default Value: 01h<br />
Access: RO<br />
Size: 8 bits<br />
Description<br />
Interrupt Connection: This field is used to communicate interrupt line routing<br />
information. POST software writes the routing information into this register as it<br />
initializes and configures the system. The value in this register indicates which<br />
input of the system interrupt controller is connected to this device’s interrupt pin.<br />
This register specifies which interrupt pin this device uses.<br />
Bit Access &<br />
Default<br />
7:0 RO<br />
01h<br />
Description<br />
Interrupt Pin: As a single function device, the PCI <strong>Express</strong> device specifies<br />
INTA as its interrupt pin.<br />
01h=INTA.<br />
Intel ® 82<strong>945G</strong>/82<strong>945G</strong>/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet 125
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