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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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Host-PCI <strong>Express</strong>* Bridge Registers (D1:F0) (<strong>Intel®</strong> 82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945P</strong>/82<strong>945P</strong>L Only)<br />

5.1.16 MLIMIT1—Memory Limit Address (D1:F0)<br />

PCI Device: 1<br />

Address Offset: 22h<br />

Default Value: 0000h<br />

Access: R/W<br />

Size: 16 bits<br />

This register controls the processor-to-PCI <strong>Express</strong> non-prefetchable memory access routing<br />

based on the following formula:<br />

MEMORY_BASE � address � MEMORY_LIMIT<br />

The upper 12 bits of the register are read/write and correspond to the upper 12 address bits<br />

A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes<br />

when read. The configuration software must initialize this register. For the purpose of address<br />

decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory<br />

address range will be at the top of a 1-MB aligned memory block.<br />

Note: Memory range covered by MBASE and MLIMIT registers are used to map non-pre-fetchable PCI<br />

<strong>Express</strong> address ranges (typically where control/status memory-mapped I/O data structures of the<br />

graphics controller will reside) and PMBASE and PMLIMIT are used to map pre-fetchable<br />

address ranges (typically, graphics local memory).<br />

This segregation allows application of USWC space attribute to be performed in a true plug-andplay<br />

manner to the pre-fetchable address range for improved processor -PCI <strong>Express</strong> memory<br />

access performance.<br />

Note: Configuration software is responsible for programming all address range registers (pre-fetchable,<br />

non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with<br />

each other and/or with the ranges covered with the main memory). There is no provision in the<br />

(G)MCH hardware to enforce prevention of overlap and operations of the system in the case of<br />

overlap may be affected.<br />

Bit Access &<br />

Default<br />

15:4 R/W<br />

000h<br />

3:0 Reserved<br />

Description<br />

Memory Address Limit (MLIMIT): This field corresponds to A[31:20] of the<br />

upper limit of the address range passed to PCI <strong>Express</strong>.<br />

122 Intel ® 82<strong>945G</strong>/82<strong>945G</strong>Z/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet

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