Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Tables
Table 4-1. Host Bridge/DRAM Controller Register Address Map (D0:F0) ....................... 61
Table 4-2. MCHBAR Register Address Map .................................................................... 90
Table 4-3. Egress Port Register Address Map ............................................................... 104
Table 5-1. Host-PCI Express* Graphics Bridge Register Address Map (D1:F0) ........... 109
Table 6-1. DMI Register Address Map ........................................................................... 161
Table 7-1. Integrated Graphics Device Register Address Map (D2:F0) ......................... 173
Table 8-1. Device 2 Function 1 Register Address Map (D2:F1) ..................................... 191
Table 9-1. Expansion Area Memory Segments .............................................................. 209
Table 9-2. Extended System BIOS Area Memory Segments ......................................... 210
Table 9-3. System BIOS Area Memory Segments ......................................................... 210
Table 9-4. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and 1-MB
TSEG ............................................................................................................................. 212
Table 9-5. SMM Space ................................................................................................... 218
Table 9-6. SMM Control .................................................................................................. 218
Table 10-1. Sample System Memory Organization with Interleaved Channels ............. 224
Table 10-2. Sample System Memory Organization with Asymmetric Channels ............ 224
Table 10-3. DDR2 DIMM Supported Configurations ...................................................... 229
Table 10-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode) ...... 230
Table 10-5. DRAM Address Translation (Dual Channel Interleaved Mode) ................... 231
Table 10-6. Concurrent SDVO / PCI Express* Configuration Strap Controls ................ 236
Table 10-7. Display Port Characteristics ........................................................................ 253
Table 10-8. Analog Port Characteristics ......................................................................... 254
Table 11-1. Absolute Minimum and Maximum Ratings .................................................. 262
Table 11-2. Non Memory Power Characteristics ............................................................ 263
Table 11-3. DDR2 Power Characteristics ....................................................................... 263
Table 11-4. Signal Groups .............................................................................................. 264
Table 11-5. DC Characteristics ....................................................................................... 267
Table 11-6. RGB/CRT DAC Display DC Characteristics: Functional Operating Range
(VCCA_DAC = 2.5 V �5%) ...................................................................................... 270
Table 12-1. Intel ® 82945G//82945GZ/82945GC/82945P/82945PL (G)MCH Ballout Sorted
by Signal Name ........................................................................................................ 275
Table 13-1. Complimentary Pins to Drive ....................................................................... 308
Table 13-2. XOR Chain Outputs ..................................................................................... 310
Table 13-3. XOR Chain 0 ................................................................................................ 311
Table 13-4. XOR Chain 1 ................................................................................................ 312
Table 13-5. XOR Chain 2 ................................................................................................ 313
Table 13-6. XOR Chain 3 ................................................................................................ 313
Table 13-7. XOR Chain 4 ................................................................................................ 314
Table 13-8. XOR Chain 5 ................................................................................................ 314
Table 13-9. XOR Chain 6 ................................................................................................ 315
Table 13-10. XOR Chain 7 .............................................................................................. 316
Table 13-11. XOR Chain 8 .............................................................................................. 316
Table 13-12. XOR Chain 9 .............................................................................................. 317
Table 13-13. XOR Pad Exclusion List............................................................................. 318
12 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet