Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

5.1.12 IOBASE1—I/O Base Address (D1:F0)
PCI Device: 1
Address Offset: 1Ch
Default Value: F0h
Access: RO
Size: 8 bits
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
This register controls the processor-to-PCI Express I/O access routing based on the following
formula:
IO_BASE � address � IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0]
are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB
boundary.
Bit Access &
Default
7:4 R/W
Fh
3:0 Reserved
5.1.13 IOLIMIT1—I/O Limit Address (D1:F0)
PCI Device: 1
Address Offset: 1Dh
Default Value: 00h
Access: R/W
Size: 8 bits
Description
I/O Address Base (IOBASE): This field corresponds to A[15:12] of the I/O
addresses passed by bridge 1 to PCI Express. BIOS must not set this register to
00h; otherwise, 0CF8h/0CFCh accesses will be forwarded to the PCI Express
hierarchy associated with this device.
This register controls the processor-to-PCI Express I/O access routing based on the following
formula:
IO_BASE � address � IO_LIMIT
Only the upper 4 bits are programmable. For the purposes of address decode, address bits A[11:0]
are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-
KB aligned address block.
Bit Access &
Default
7:4 R/W
0h
3:0 Reserved
Description
I/O Address Limit (IOLIMIT): This field corresponds to A[15:12] of the I/O
address limit of device 1. Devices between this upper limit and IOBASE1 will be
passed to the PCI Express hierarchy associated with this device.
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 119