Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

5.1.7 CL1—Cache Line Size (D1:F0)
PCI Device: 1
Address Offset: 0Ch
Default Value: 00h
Access: R/W
Size: 8 bits
Bit Access &
Default
7:0 R/W
00h
5.1.8 HDR1—Header Type (D1:F0)
PCI Device: 1
Address Offset: 0Eh
Default Value: 01h
Access: RO
Size: 8 bits
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
Description
Cache Line Size (Scratch pad): This field is implemented by PCI Express*
devices as a read-write field for legacy compatibility purposes but has no impact
on any PCI Express device functionality.
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit Access &
Default
7:0 RO
01h
Description
Header Type Register (HDR): This field returns 01h to indicate that this is a single
function device with bridge header layout.
5.1.9 PBUSN1—Primary Bus Number (D1:F0)
PCI Device: 1
Address Offset: 18h
Default Value: 00h
Access: RO
Size: 8 bits
This register identifies that this “virtual” Host-PCI Express bridge is connected to PCI bus 0.
Bit Access &
Default
7:0 RO
00h
Description
Primary Bus Number (BUSN): Configuration software typically programs this field
with the number of the bus on the primary side of the bridge. Since device 1 is an
internal device and its primary bus is always 0, these bits are read only and are
hardwired to 0s.
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 117