Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
Bit Access &
Default
2 R/W
0b
1 R/W
0b
0 R/W
0b
Description
Bus Master Enable (BME): This bit controls the ability of the PCI Express port to
forward memory and I/O read/write requests in the upstream direction.
0 = Disable. This device is prevented from making memory or I/O requests to its
primary bus. Note that according to PCI Local Bus Specification, as MSI
interrupt messages are in-band memory writes, disabling the bus master
enable bit prevents this device from generating MSI interrupt messages or
passing them from its secondary bus to its primary bus. Upstream memory
writes/reads, I/O writes/reads, peer writes/reads, and MSIs will all be treated
as invalid cycles. Writes are forwarded to memory address 0h with byte
enables de-asserted. Reads will be forwarded to memory address 0h and
will return Unsupported Request status (or Master abort) in its completion
packet.
1 = Enable. This device is allowed to issue requests to its primary bus.
Completions for previously issued memory read requests on the primary
bus will be issued when the data is available.
This bit does not affect forwarding of completions from the primary interface to
the secondary interface.
Memory Access Enable (MAE):
0 = Disable. All of device 1’s memory space is disabled.
1 = Enable the Memory and Pre-fetchable memory address ranges defined in
the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
IO Access Enable (IOAE):
0 = Disable. All of device 1’s I/O space is disabled.
1 = Enable the I/O address range defined in the IOBASE1, and IOLIMIT1
registers.
114 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet