Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only) 5.1 Configuration Register Details (D1:F0) 5.1.1 VID1—Vendor Identification (D1:F0) PCI Device: 1 Address Offset: 00h Default Value: 8086h Access: RO Size: 16 bits This register, combined with the Device Identification register, uniquely identifies any PCI device. Bit Access & Default 15:0 RO 8086 h 5.1.2 DID1—Device Identification (D1:F0) PCI Device: 1 Address Offset: 02h Default Value: 2771h Access: RO Size: 16 bits Description Vendor Identification (VID1): This field provides the PCI standard identification for Intel. This register, combined with the Vendor Identification register, uniquely identifies any PCI device. Bit Access & Default 15:0 RO 2581h Description Device Identification Number (DID1): This field is an identifier assigned to the (G)MCH device 1 (virtual PCI-to-PCI bridge, PCI Express* graphics port). 112 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
5.1.3 PCICMD1—PCI Command (D1:F0) PCI Device: 1 Address Offset: 04h Default Value: 0000h Access: RO, R/W Size: 16 bits Bit Access & Default 15:11 Reserved 10 R/W 0b 9 RO 0b 8 R/W 0b 7 Reserved 6 R/WO 0b 5 RO 0b 4 RO 0b 3 RO 0b Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only) INTA Assertion Disable: Description 0 = This device is permitted to generate INTA interrupt messages. 1 = This device is prevented from generating interrupt messages. Any INTA emulation interrupts already asserted must be de-asserted when this bit is set. This bit only affects interrupts generated by the device (PCI INTA from a PME or Hot Plug event) controlled by this register. It does not affect upstream MSIs, upstream PCI INTA-INTD assert and de-assert messages. Fast Back-to-Back Enable (FB2B): Hardwired to 0. Not Applicable or Implemented. SERR Message Enable (SERRE1): This bit is an enable bit for Device 1 SERR messaging. The (G)MCH communicates the SERR# condition by sending a SERR message to the Intel ® ICH7. This bit, when set, enables reporting of nonfatal and fatal errors to the Root Complex. Note that errors are reported if enabled either through this bit or through the PCI Express* specific bits in the Device Control register. 0 = Disable. The SERR message is generated by the (G)MCH for Device 1 only under conditions enabled individually through the Device Control register. 1 = Enable. The (G)MCH is enabled to generate SERR messages that will be sent to the ICH7 for specific Device 1 error conditions generated/detected on the primary side of the virtual PCI-to-PCI Express bridge (not those received by the secondary side). The error status is reported in the PCISTS1 register. Parity Error Enable (PERRE): This bit controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set. 0 = Disable. Master Data Parity Error bit in PCI Status register cannot be set. 1 = Enable. Master Data Parity Error bit in PCI Status register can be set. VGA Palette Snoop: Hardwired to 0. Not Applicable or Implemented. Memory Write and Invalidate Enable (MWIE): Hardwired to 0. Not Applicable or Implemented. Special Cycle Enable (SCE): Hardwired to 0. Not Applicable or Implemented. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 113
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- Page 67 and 68: 4.1.7 MLT—Master Latency Timer (D
- Page 69 and 70: 4.1.12 EPBAR—Egress Port Base Add
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- Page 83 and 84: 4.1.25 LAC—Legacy Access Control
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- Page 87 and 88: 4.1.29 ERRSTS—Error Status (D0:F0
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- Page 95 and 96: 4.2.7 C0DCLKDIS—Channel A DRAM Cl
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- Page 107 and 108: 4.3.3 EPLE1A—EP Link Entry 1 Addr
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- Page 115 and 116: 5.1.4 PCISTS1—PCI Status (D1:F0)
- Page 117 and 118: 5.1.7 CL1—Cache Line Size (D1:F0)
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- Page 121 and 122: 5.1.15 MBASE1—Memory Base Address
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- Page 127 and 128: Bit Access & Default 2 R/W 0b 1 R/W
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- Page 133 and 134: 5.1.29 MA—Message Address (D1:F0)
- Page 135 and 136: 5.1.33 DCAP—Device Capabilities (
- Page 137 and 138: 5.1.35 DSTS—Device Status (D1:F0)
- Page 139 and 140: 5.1.37 LCTL—Link Control (D1:F0)
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Host-PCI <strong>Express</strong>* Bridge Registers (D1:F0) (<strong>Intel®</strong> 82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945P</strong>/82<strong>945P</strong>L Only)<br />
5.1 Configuration Register Details (D1:F0)<br />
5.1.1 VID1—Vendor Identification (D1:F0)<br />
PCI Device: 1<br />
Address Offset: 00h<br />
Default Value: 8086h<br />
Access: RO<br />
Size: 16 bits<br />
This register, combined with the Device Identification register, uniquely identifies any PCI<br />
device.<br />
Bit Access &<br />
Default<br />
15:0 RO<br />
8086 h<br />
5.1.2 DID1—Device Identification (D1:F0)<br />
PCI Device: 1<br />
Address Offset: 02h<br />
Default Value: 2771h<br />
Access: RO<br />
Size: 16 bits<br />
Description<br />
Vendor Identification (VID1): This field provides the PCI standard identification for<br />
Intel.<br />
This register, combined with the Vendor Identification register, uniquely identifies any PCI<br />
device.<br />
Bit Access &<br />
Default<br />
15:0 RO<br />
2581h<br />
Description<br />
Device Identification Number (DID1): This field is an identifier assigned to the<br />
(G)MCH device 1 (virtual PCI-to-PCI bridge, PCI <strong>Express</strong>* graphics port).<br />
112 Intel ® 82<strong>945G</strong>/82<strong>945G</strong>Z/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet
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