Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

4.3.3 EPLE1A—EP Link Entry 1 Address
MMIO Range: EPBAR
Address Offset: 058–05Fh
Default Value: 00000000_00000000h
Access: R/WO
Size: 64 bits
Host Bridge/DRAM Controller Registers (D0:F0)
This register is the second part of a Link Entry that declares an internal link to another Root
Complex Element.
Bit Access &
Default
63:32 Reserved
31:12 R/WO
0 0000h
11:0 Reserved
Description
Link Address: This field provides the memory mapped base address of the
RCRB that is the target element (DMI) for this link entry.
4.3.4 EPLE2D—EP Link Entry 2 Description
MMIO Range: EPBAR
Address Offset: 060–63h
Default Value: 02000002h
Access: RO, R/WO
Size: 32 bits
This register provides the first part of a Link Entry that declares an internal link to another Root
Complex Element.
Bit Access &
Default
31:24 RO
02h
23:16 R/WO
00h
15:2 Reserved
1 RO
1b
0 R/WO
0b
Description
Target Port Number: This field specifies the port number associated with the
element targeted by this link entry (PCI Express). The target port number is with
respect to the component that contains this element as specified by the target
component ID.
Target Component ID: This field identifies the physical or logical component that
is targeted by this link entry. A value of 0 is reserved; component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
Link Type: This bit indicates that the link points to configuration space of the
integrated device that controls the x16 root port. The link address specifies the
configuration address (segment, bus, device, function) of the target root port.
Link Valid:
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 107