Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Host Bridge/DRAM Controller Registers (D0:F0) 4.2.20 C1DRT1—Channel B DRAM Timing Register 1 MMIO Range: MCHBAR Address Offset: 194–197h Default Value: 02903D22h Access: RO Size: 32 bits The operation of this register is detailed in the description for the C0DRT1 register. 4.2.21 C1DRC0—Channel B DRAM Controller Mode 0 MMIO Range: MCHBAR Address Offset: 1A0–1A3h Default Value: 4000280_00ssh (s = strap dependent) Access: RO, R/W Size: 32 bits The operation of this register is detailed in the description for the C0DRC0 register. 4.2.22 C1DRC1—Channel B DRAM Controller Mode 1 MMIO Range: MCHBAR Address Offset: 1A4–1A7h Default Value: 00000000h Access: RO, R/W, R/W/L Size: 32 bits The operation of this register is detailed in the description for the C0DRC1 register. 4.2.23 PMCFG—Power Management Configuration PCI Device: MCHBAR Address Offset: F10–F13h Default: 00000000h Access: RO, R/W Size: 32 bits Bit Access & Default 31:5 Reserved 4 R/W 0b Description Enhanced Power Management Features Enable: 0 = Legacy power management mode 1 = Reserved. 3:0 Reserved 102 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
4.2.24 PMSTS—Power Management Status PCI Device: MCHBAR Address Offset: F14–F17h Default: 00h Access: R/WC/S Size: 32 bits This register is reset by PWROK only. Bit Access & Default 31:2 Reserved 1 R/WC/S 0b 0 R/WC/S 0b Host Bridge/DRAM Controller Registers (D0:F0) Description Channel B in self-refresh: This bit is set by power management hardware after Channel B is placed in self refresh as a result of a Power State or a Warm Reset sequence. This bit is cleared by power management hardware before starting Channel B self refresh exit sequence initiated by a power management exit. This bit is cleared by the BIOS in a warm reset (Reset# asserted while PWROK is asserted) exit sequence. 0 = Channel B not ensured to be in self refresh. 1 = Channel B in self refresh. Channel A in Self-refresh: This bit is set by power management hardware after Channel A is placed in self refresh as a result of a Power State or a Reset Warn sequence. This bit is cleared by power management hardware before starting Channel A self refresh exit sequence initiated by a power management exit. This bit is cleared by the BIOS in a warm reset (Reset# asserted while PWROK is asserted) exit sequence. 0 = Channel A not ensured to be in self refresh. 1 = Channel A in self refresh. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 103
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- Page 55 and 56: 3.4 Routing Configuration Accesses
- Page 57 and 58: 3.4.2.2 DMI Configuration Accesses
- Page 59 and 60: Bit Access & Default 10:8 R/W 000b
- Page 61 and 62: Host Bridge/DRAM Controller Registe
- Page 63 and 64: 4.1 Device 0 Configuration Register
- Page 65 and 66: 4.1.4 PCISTS—PCI Status (D0:F0) P
- Page 67 and 68: 4.1.7 MLT—Master Latency Timer (D
- Page 69 and 70: 4.1.12 EPBAR—Egress Port Base Add
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- Page 75 and 76: Host Bridge/DRAM Controller Registe
- Page 77 and 78: 4.1.19 PAM1—Programmable Attribut
- Page 79 and 80: 4.1.21 PAM3—Programmable Attribut
- Page 81 and 82: 4.1.23 PAM5—Programmable Attribut
- Page 83 and 84: 4.1.25 LAC—Legacy Access Control
- Page 85 and 86: Host Bridge/DRAM Controller Registe
- Page 87 and 88: 4.1.29 ERRSTS—Error Status (D0:F0
- Page 89 and 90: 4.1.31 SKPD—Scratchpad Data (D0:F
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- Page 95 and 96: 4.2.7 C0DCLKDIS—Channel A DRAM Cl
- Page 97 and 98: 4.2.9 C0DRT1—Channel A DRAM Timin
- Page 99 and 100: Bit Access & Default 6:4 R/W 000b 3
- Page 101: Host Bridge/DRAM Controller Registe
- Page 105 and 106: 4.3.1 EPESD—EP Element Self Descr
- Page 107 and 108: 4.3.3 EPLE1A—EP Link Entry 1 Addr
- Page 109 and 110: Host-PCI Express* Bridge Registers
- Page 111 and 112: Address Offset Host-PCI Express* Br
- Page 113 and 114: 5.1.3 PCICMD1—PCI Command (D1:F0)
- Page 115 and 116: 5.1.4 PCISTS1—PCI Status (D1:F0)
- Page 117 and 118: 5.1.7 CL1—Cache Line Size (D1:F0)
- Page 119 and 120: 5.1.12 IOBASE1—I/O Base Address (
- Page 121 and 122: 5.1.15 MBASE1—Memory Base Address
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- Page 125 and 126: 5.1.20 INTRLINE1—Interrupt Line (
- Page 127 and 128: Bit Access & Default 2 R/W 0b 1 R/W
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- Page 131 and 132: Host-PCI Express* Bridge Registers
- Page 133 and 134: 5.1.29 MA—Message Address (D1:F0)
- Page 135 and 136: 5.1.33 DCAP—Device Capabilities (
- Page 137 and 138: 5.1.35 DSTS—Device Status (D1:F0)
- Page 139 and 140: 5.1.37 LCTL—Link Control (D1:F0)
- Page 141 and 142: 5.1.39 SLOTCAP—Slot Capabilities
- Page 143 and 144: 5.1.41 SLOTSTS—Slot Status (D1:F0
- Page 145 and 146: 5.1.43 RSTS—Root Status (D1:F0) P
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Host Bridge/DRAM Controller Registers (D0:F0)<br />
4.2.20 C1DRT1—Channel B DRAM Timing Register 1<br />
MMIO Range: MCHBAR<br />
Address Offset: 194–197h<br />
Default Value: 02903D22h<br />
Access: RO<br />
Size: 32 bits<br />
The operation of this register is detailed in the description for the C0DRT1 register.<br />
4.2.21 C1DRC0—Channel B DRAM Controller Mode 0<br />
MMIO Range: MCHBAR<br />
Address Offset: 1A0–1A3h<br />
Default Value: 4000280_00ssh (s = strap dependent)<br />
Access: RO, R/W<br />
Size: 32 bits<br />
The operation of this register is detailed in the description for the C0DRC0 register.<br />
4.2.22 C1DRC1—Channel B DRAM Controller Mode 1<br />
MMIO Range: MCHBAR<br />
Address Offset: 1A4–1A7h<br />
Default Value: 00000000h<br />
Access: RO, R/W, R/W/L<br />
Size: 32 bits<br />
The operation of this register is detailed in the description for the C0DRC1 register.<br />
4.2.23 PMCFG—Power Management Configuration<br />
PCI Device: MCHBAR<br />
Address Offset: F10–F13h<br />
Default: 00000000h<br />
Access: RO, R/W<br />
Size: 32 bits<br />
Bit Access &<br />
Default<br />
31:5 Reserved<br />
4 R/W<br />
0b<br />
Description<br />
Enhanced Power Management Features Enable:<br />
0 = Legacy power management mode<br />
1 = Reserved.<br />
3:0 Reserved<br />
102 Intel ® 82<strong>945G</strong>/82<strong>945G</strong>Z/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet
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