Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Host Bridge/DRAM Controller Registers (D0:F0)
4.2.11 C0DRC1—Channel A DRAM Controller Mode 1
Bus/Dev/Func/Type: 0/0/0/MCHBAR
Address Offset: 124–127h
Default Value: 00000000h
Access: R/W
Size: 32 bits
Bit Access &
Default
31 R/W
0b
30:0 Intel Reserved
Description
Enhanced Addressing Enable (ENHADE):
0 = Enhanced Addressing mode disabled. The DRAM address map follows the
standard address map.
1 = Enhanced Address mode enabled. The DRAM address map follows the
enhanced address map.
4.2.12 C1DRB0—Channel B DRAM Rank Boundary Address 0
MMIO Range: MCHBAR
Address Offset: 180h
Default Value: 00h
Access: R/W
Size: 8 bits
The operation of this register is detailed in the description for the C0DRB0 register.
4.2.13 C1DRB1—Channel B DRAM Rank Boundary Address 1
MMIO Range: MCHBAR
Address Offset: 181h
Default Value: 00h
Access: R/W
Size: 8 bits
The operation of this register is detailed in the description for the C0DRB0 register.
4.2.14 C1DRB2—Channel B DRAM Rank Boundary Address 2
MMIO Range: MCHBAR
Address Offset: 182h
Default Value: 00h
Access: R/W
Size: 8 bits
The operation of this register is detailed in the description for the C0DRB0 register.
100 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet