DATA SHEET - Glyn High-Tech Distribution
DATA SHEET - Glyn High-Tech Distribution DATA SHEET - Glyn High-Tech Distribution
HX8346-A(T)240RGBx320 dots, 262K color TFT controller driverDATA SHEET V01SON7-0: Specify the valid source output start time in 1-line driving period. The periodtime is defined as SYSCLK clock number. (Please note that the setting “00h”and “01h” is inhibited).GON7-0: Specify the valid gate output start time in 1-line driving period. The periodtime is defined as SYSCLK clock number in internal clock display mode.The period time is defined as setting value x 8 DOTCLK clock number inexternal clock display mode. (Please note that the setting “00h”,“01h”, “02h”is inhibited).GOF7-0: Specify the gate output end time in 1-line driving period. The period time isdefined as SYSCLK clock number in internal clock display mode. The periodtime is defined as setting value x 8 DOTCLK clock number in external clockdisplay mode. (Please note that the GOF8-0 ≤ HCK-1).7.36 BGP Control Register (R42h)BGP[3:0]: band gap voltage controlFigure 7. 56 BGP Control 1 Register (R42h)BGP[3:0] VBGP output4’b0000 1.1824’b0001 1.1924’b0010 1.2004’b0011 1.2104’b0100 1.2214’b0101 1.2284’b0110 1.2364’b0111 1.2464’b1000 1.2564’b1001 1.2644’b1010 1.2744’b1011 1.2824’b1100 1.2924’b1101 1.3004’b1110 1.3084’b1111 1.315Himax ConfidentialThis information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosedin whole or in part without prior written permission of Himax.-P.109-July, 2007
HX8346-A(T)240RGBx320 dots, 262K color TFT controller driver7.37 Vcom Control 1 Register (R43h)DATA SHEET V01Figure 7. 57 Vcom Control 1 Register (R43h)VCOMG:When VCOMG = 1, VCOML voltage can output to negative voltage (1.0V ~ VCI+0.5V).When VCOMG = 0, VCOML outputs VSSA and VDV(4-0) setting are invalid. Then,low power consumption is accomplished.7.38 Vcom Control 2 Register (R44h)Figure 7. 58 Vcom Control 2 RegisterVCM(6-0):Set the VCOMH voltage (High level voltage of VCOM) It is possible to amplify from0.4 to 0.98 times of VREG1 voltage.Himax ConfidentialThis information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosedin whole or in part without prior written permission of Himax.-P.110-July, 2007
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HX8346-A(T)240RGBx320 dots, 262K color TFT controller driver<strong>DATA</strong> <strong>SHEET</strong> V01SON7-0: Specify the valid source output start time in 1-line driving period. The periodtime is defined as SYSCLK clock number. (Please note that the setting “00h”and “01h” is inhibited).GON7-0: Specify the valid gate output start time in 1-line driving period. The periodtime is defined as SYSCLK clock number in internal clock display mode.The period time is defined as setting value x 8 DOTCLK clock number inexternal clock display mode. (Please note that the setting “00h”,“01h”, “02h”is inhibited).GOF7-0: Specify the gate output end time in 1-line driving period. The period time isdefined as SYSCLK clock number in internal clock display mode. The periodtime is defined as setting value x 8 DOTCLK clock number in external clockdisplay mode. (Please note that the GOF8-0 ≤ HCK-1).7.36 BGP Control Register (R42h)BGP[3:0]: band gap voltage controlFigure 7. 56 BGP Control 1 Register (R42h)BGP[3:0] VBGP output4’b0000 1.1824’b0001 1.1924’b0010 1.2004’b0011 1.2104’b0100 1.2214’b0101 1.2284’b0110 1.2364’b0111 1.2464’b1000 1.2564’b1001 1.2644’b1010 1.2744’b1011 1.2824’b1100 1.2924’b1101 1.3004’b1110 1.3084’b1111 1.315Himax ConfidentialThis information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosedin whole or in part without prior written permission of Himax.-P.109-July, 2007