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DATA SHEET - Glyn High-Tech Distribution

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HX8346-A(T)240RGBx320 dots, 262K color TFT controller driver<strong>DATA</strong> <strong>SHEET</strong> V01ISC[3:0] :Specify the scan cycle of gate driver when PTG1-0=10 in non-display area.Then scan cycle is set to an odd number from 0~31.The polarity is inverted everyscan cycle.ISC3 ISC2 ISC1 ISC0 Scan Cycle f FLM = 70Hz0 0 0 0 0 frame -0 0 0 1 3 frames 50 ms0 0 1 0 5 frames 84 ms0 0 1 1 7 frames 117 ms0 1 0 0 9 frames 150 ms0 1 0 1 11 frames 184 ms0 1 1 0 13 frames 217 ms0 1 1 1 15 frames 251 ms1 0 0 0 17 frames 284 ms1 0 0 1 19 frames 317 ms1 0 1 0 21 frames 351 ms1 0 1 1 23 frames 384 ms1 1 0 0 25 frames 418 ms1 1 0 1 27 frames 451 ms1 1 1 0 29 frames 484 ms1 1 1 1 31 frames 518 ms7.30 RGB Interface Control 1 Register (R38h)Figure 7. 48 RGB Interface Control 1 Register (R38h)This command is used to set RGB interface related registerEPL: Specify the polarity of Enable pin in RGB interface mode.EPL=0, the Enable is<strong>High</strong> active; EPL=1, the Enable is Low activeVSPL: The polarity of VSYNC pin. When VSPL=0, the VSYNC pin is Low active.When VSPL=1, the VSYNC pin is <strong>High</strong> active.HSPL: The polarity of HSYNC pin. When HSPL=0, the HSYNC pin is Low active.When HSPL=1, the HSYNC pin is <strong>High</strong> active.DPL: The polarity of DOTCLK pin. When DPL=0, the data is read on the rising edgeof DOTCLK signal. When DPL=1, the data is read on the falling edge of DOTCLKsignal.Himax ConfidentialThis information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosedin whole or in part without prior written permission of Himax.-P.105-July, 2007

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