IAR PowerPac RTOS User Guide

InterruptsIntroductionIn this chapter, you will find a very basic description about using interrupt service routines (ISRs) in cooperation withIAR PowerPac RTOS. Specific details for your CPU and compiler may be found in the CPU & Compiler Specificsmanual of the IAR PowerPac RTOS documentation.Interrupts are interruptions of a program caused by hardware. When an interrupt occurs, the CPU saves its registers andexecutes a subroutine called an interrupt service routine, or ISR. After the ISR is completed, the program returns tothe highest-priority task in the READY state. Normal interrupts are maskable; they can occur at any time unless theyare disabled with the CPU's "disable interrupt" instruction. ISRs are also nestable - they can be recognized and executedwithin other ISRs.There are several good reasons for using interrupt routines. They can respond very quickly to external events such asthe status change on an input, the expiration of a hardware timer, reception or completion of transmission of a charactervia serial interface, or other types of events. Interrupts effectively allow events to be processed as they occur.Interrupt latencyInterrupt latency is the time between an interrupt request and the execution of the first instruction of the interrupt serviceroutine.Every computer system has an interrupt latency. The latency depends on various factors and differs even on the samecomputer system. The value that one is typically interested in is the worst case interrupt latency.The interrupt latency is the sum of a lot of different smaller delays explained below.CAUSES OF INTERRUPT LATENCIES●●●●●The first delay is typically in the hardware: The interrupt request signal needs to be synchronized to the CPU clock.Depending on the synchronization logic, typically up to 3 CPU cycles can be lost before the interrupt request hasreached the CPU core.The CPU will typically complete the current instruction. This instruction can take a lot of cycles; on most systems,divide, push-multiple, or memory-copy instructions are the instructions which require most clock cycles. On top ofthe cycles required by the CPU, there are in most cases additional cycles required for memory access. In an ARM7system, the instruction STMDB SP!,{R0-R11,LR}; (Push parameters and perm. register) is typically the worstcase instruction. It stores 13 32-bit registers on the stack. The CPU requires 15 clock cycles.The memory system may require additional cycles for wait states.After the current instruction is completet, the CPU performs a mode switch or pushes registers (typically, PC andflag registers) on the stack. In general, modern CPUs (such as ARM) perform a mode switch, which requires lessCPU cycles than saving registers.Pipeline fillMost modern CPUs are pipelined. Execution of an instruction happens in various stages of the pipeline. Aninstruction is executed when it has reached its final stage of the pipeline. Because the mode switch has flushed thepipeline, a few extra cycles are required to refill the pipeline.ADDITIONAL CAUSES FOR INTERRUPT LATENCIESThere can be additional causes for interrupt latencies.These depend on the type of system used, but we list a few of them.●Latencies caused by cache line fill.If the memory system has one or multiple caches, these may not contain the required data. In this case, not only therequired data is loaded from memory, but in a lot of cases a complete line fill needs to be performed, readingmultiple words from memory.PPRTOS-2 99