IAR PowerPac RTOS User Guide

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We recommend using OS_EnterIntStack() and OS_LeaveIntStack() even if there is currently no additionalbenefit for your specific CPU, because code that uses them might reduce stack size on another CPU or a new versionof IAR PowerPac RTOS with support for an interrupt stack for your CPU. For details about interrupt stacks, see theCPU & Compiler Specifics manual of IAR PowerPac RTOS documentation.Stacks API function overviewRoutineOS_GetStackSpace()Table 112: Stacks API overviewOS_GetStackSpace()DescriptionReturns the unused portion of a task stack.Prototypeint OS_GetStackSpace (OS_TCB* pTask);ParameterDescriptionpTaskTable 113: OS_GetStackSpace() parameter listReturn valueThe unused portion of the task stack in bytes.Additional InformationIn most cases, the stack size required by a task cannot be easily calculated, because it takes quite some time to calculatethe worst-case nesting and the calculation itself is difficult.However, the required stack size can be calculated using the function OS_GetStackSpace(), which returns thenumber of unused bytes on the stack. If there is a lot of space left, you can reduce the size of this stack and vice versa.This function is only available in the debug and stack check builds of IAR PowerPac RTOS, because only these buildsinitialize the stack space used for the tasks.ImportantThis routine does not reliably detect the amount of stack space left, because it can only detect modified bytes on thestack. Unfortunately, space used for register storage or local variables is not always modified. In most cases, thisroutine will detect the correct amount of stack bytes, but in case of doubt, be generous with your stack space or useother means to verify that the allocated stack space is sufficient.ExampleDescriptionReturns the unused portion of a task stack.The task who's stack space is to be checked.NULL means current task.void CheckSpace(void) {printf("Unused Stack[0] %d", OS_GetStackSpace(&TCB[0]);OS_Delay(1000);printf("Unused Stack[1] %d", OS_GetStackSpace(&TCB[1]);OS_Delay(1000);}98IAR PowerPac RTOSfor ARM CoresPPRTOS-2
InterruptsIntroductionIn this chapter, you will find a very basic description about using interrupt service routines (ISRs) in cooperation withIAR PowerPac RTOS. Specific details for your CPU and compiler may be found in the CPU & Compiler Specificsmanual of the IAR PowerPac RTOS documentation.Interrupts are interruptions of a program caused by hardware. When an interrupt occurs, the CPU saves its registers andexecutes a subroutine called an interrupt service routine, or ISR. After the ISR is completed, the program returns tothe highest-priority task in the READY state. Normal interrupts are maskable; they can occur at any time unless theyare disabled with the CPU's "disable interrupt" instruction. ISRs are also nestable - they can be recognized and executedwithin other ISRs.There are several good reasons for using interrupt routines. They can respond very quickly to external events such asthe status change on an input, the expiration of a hardware timer, reception or completion of transmission of a charactervia serial interface, or other types of events. Interrupts effectively allow events to be processed as they occur.Interrupt latencyInterrupt latency is the time between an interrupt request and the execution of the first instruction of the interrupt serviceroutine.Every computer system has an interrupt latency. The latency depends on various factors and differs even on the samecomputer system. The value that one is typically interested in is the worst case interrupt latency.The interrupt latency is the sum of a lot of different smaller delays explained below.CAUSES OF INTERRUPT LATENCIES●●●●●The first delay is typically in the hardware: The interrupt request signal needs to be synchronized to the CPU clock.Depending on the synchronization logic, typically up to 3 CPU cycles can be lost before the interrupt request hasreached the CPU core.The CPU will typically complete the current instruction. This instruction can take a lot of cycles; on most systems,divide, push-multiple, or memory-copy instructions are the instructions which require most clock cycles. On top ofthe cycles required by the CPU, there are in most cases additional cycles required for memory access. In an ARM7system, the instruction STMDB SP!,{R0-R11,LR}; (Push parameters and perm. register) is typically the worstcase instruction. It stores 13 32-bit registers on the stack. The CPU requires 15 clock cycles.The memory system may require additional cycles for wait states.After the current instruction is completet, the CPU performs a mode switch or pushes registers (typically, PC andflag registers) on the stack. In general, modern CPUs (such as ARM) perform a mode switch, which requires lessCPU cycles than saving registers.Pipeline fillMost modern CPUs are pipelined. Execution of an instruction happens in various stages of the pipeline. Aninstruction is executed when it has reached its final stage of the pipeline. Because the mode switch has flushed thepipeline, a few extra cycles are required to refill the pipeline.ADDITIONAL CAUSES FOR INTERRUPT LATENCIESThere can be additional causes for interrupt latencies.These depend on the type of system used, but we list a few of them.●Latencies caused by cache line fill.If the memory system has one or multiple caches, these may not contain the required data. In this case, not only therequired data is loaded from memory, but in a lot of cases a complete line fill needs to be performed, readingmultiple words from memory.PPRTOS-2 99
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IAR PowerPac RTOSUser GuidePPRTOS-2
Page 3 and 4:
PrefaceWelcome to the IAR PowerPac
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ContentsPreface ...................
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ContentsOS_WaitCSema() ............
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ContentsOS_LeaveInterrupt() .......
Page 11 and 12:
Introduction to IAR PowerPacRTOSWha
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Basic conceptsTasksIn this context,
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Basic conceptsPREEMPTIVES MULTITASK
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Basic conceptsMAILBOXES AND QUEUESA
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Basic conceptsThe active task may b
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Basic conceptsThe flowchart below i
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Basic conceptsLIST OF LIBRARIESIn y
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Task routinesIntroductionA task tha
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Task routinesOS_CREATETASK() can be
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Task routinesExampleThe following e
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Task routinesExampleint sec,min;voi
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Task routinesAdditional Information
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Task routinesReturn valueOS_TASKID:
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Software timersSoftware timerA soft
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Software timers#define OS_CREATETIM
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Software timersOS_SetTimerPeriod()D
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Software timersAdditional Informati
Page 45 and 46:
Software timersAdditional Informati
Page 47 and 48: Software timersExampleOS_TIMER TIME
Page 49 and 50: Resource semaphoresIntroductionReso
Page 51 and 52: Resource semaphoresResource semapho
Page 53 and 54: Resource semaphoresOS_Request()Desc
Page 55 and 56: Counting SemaphoresIntroductionCoun
Page 57 and 58: Counting SemaphoresPrototypevoid OS
Page 59 and 60: Counting SemaphoresReturn value0: I
Page 61 and 62: MailboxesWhy mailboxes?In the prece
Page 63 and 64: MailboxesMailboxes API function ove
Page 65 and 66: MailboxesExampleSingle-byte mailbox
Page 67 and 68: MailboxesPrototypevoid OS_GetMail (
Page 69 and 70: MailboxesOS_WaitMail()DescriptionWa
Page 71 and 72: QueuesWhy queues?In the preceding c
Page 73 and 74: QueuesReturn valueThe size of the r
Page 75 and 76: QueuesExamplestatic void MemoryTask
Page 77 and 78: Task eventsIntroductionTask events
Page 79 and 80: Task eventsExampleOS_WaitEventTimed
Page 81 and 82: Task eventsPrototypechar OS_ClearEv
Page 83 and 84: Event objectsIntroductionEvent obje
Page 85 and 86: Event objectsExampleif (OS_EVENT_Wa
Page 87 and 88: Event objectsExampleOS_EVENT_Reset(
Page 89 and 90: Heap type memory managementANSI C o
Page 91 and 92: Fixed block size memory poolsIntrod
Page 93 and 94: Fixed block size memory poolsProtot
Page 95 and 96: Fixed block size memory poolsProtot
Page 97: StacksIntroductionThe stack is the
Page 101 and 102: InterruptsRules for interrupt handl
Page 103 and 104: InterruptsOS_LeaveInterruptNoSwitch
Page 105 and 106: InterruptsNesting interrupt routine
Page 107 and 108: Critical RegionsIntroductionCritica
Page 109 and 110: System variablesIntroductionThe sys
Page 111 and 112: Configuration for your targetsystem
Page 113 and 114: Time measurementIntroductionIAR Pow
Page 115 and 116: Time measurementPrototypeU32 OS_Get
Page 117 and 118: Time measurementPrototypeOS_U32 OS_
Page 119 and 120: RTOS-aware debuggingThis chapter de
Page 121 and 122: RTOS-aware debuggingTimersA softwar
Page 123 and 124: DebuggingRuntime errorsSome error c
Page 125 and 126: DebuggingValue Define Description17
Page 127 and 128: Performance and resource usageThis
Page 129 and 130: Performance and resource usageThe c
Page 131 and 132: Performance and resource usage*/sta
Page 133 and 134: ReentranceAll routines that can be
Page 135 and 136: LimitationsThe following limitation
Page 137 and 138: Source code of kernel and libraryIn
Page 139 and 140: Additional modulesKeyboard manager:
Page 141 and 142: FAQ (frequently asked questions)Q:
Page 143 and 144: GlossaryActive TaskCooperativemulti
Page 145 and 146: IndexIndexAAdditional modules . . .
Page 147: IndexOS_WaitSingleEventTimed(). . .
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IAR PowerPac RTOS User Guide

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