IAR PowerPac RTOS User Guide

●●●●●Latencies caused by cache write back.A cache miss may cause a line to be replaced. If this line is marked as dirty, it needs to be written back to mainmemory, causing an additional delay.Latencies caused by MMU translation table walks.Translation table walks can take a considerable amount of time, especially as they involve potentially slow mainmemory accesses. In real-time interrupt handlers, translation table walks caused by the TLB not containingtranslations for the handler and/or the data it accesses can increase interrupt latency significantly.Application program.Of course, the application program can cause additional latencies by disabling interrupts. This can make sense insome situations, but of course causes add. latencies.Interrupt routines.On most systems, one interrupt disables further interrupts. Even if the interrupts are re-enabled in the ISR, thistakes a few instructions, causing add. latency.RTOS (Real-time Operating system).An RTOS also needs to temporarily disable the interrupts which can call API-functions of the RTOS. SomeRTOSes disable all interrupts, effectively increasing interrupt latencies for all interrupts, some (like IAR PowerPacRTOS) disable only low-priority interrupts and do thereby not affect the latency of high priority interrupts.Zero interrupt latencyZero interrupt latency in the strict sense is not possible as explained above. What we mean when we say "Zero interruptlatency" is that the latency of high-priority interrupts is not affected by the RTOS; a system using IAR PowerPac RTOSwill have the same worst-case interrupt latency for high priority interrupts as a system running without IAR PowerPacRTOS.High / low priority interruptsMost CPUs support interrupts with different priorities. Different priorities have two effects:● If different interrupts occur simultaneously, the interrupt with higher priority takes precedence and its ISR isexecuted first.● Interrupts can never be interrupted by other interrupts of the same or lower level of priority.How many different levels of interrupts there are depend on the CPU and the interrupt controller. Details are explainedin the CPU/MCU/SOC manuals and the CPU & Compiler Specifics manual of IAR PowerPac RTOS. IAR PowerPacRTOS distinguishes two different levels of interrupts: High / Low priority interrupts. The IAR PowerPac RTOS portspecific documentation explains where "the line is drawn", which interrupts are considered high and which interruptsare considered low priority. In general, the differences are:Low-priority interrupts●●May call IAR PowerPac RTOS API functionsLatencies caused by IAR PowerPac RTOSHigh-priority interrupts●●May not call IAR PowerPac RTOS API functionsNo Latencies caused by IAR PowerPac RTOS (Zero latency)Example of different interrupt priority levelsARM CPUs support normal interrupts (IRQ) and fast interrupt (FIQ). Using IAR PowerPac RTOS, the FIQ is treatedas “High priority interrupt”.100IAR PowerPac RTOSfor ARM CoresPPRTOS-2