Implementing Hardware and Software for an ARM Cortex-M1 in FPGA

Implementing Hardware and Software for 

an ARM Cortex-M1 in FPGA 

Mike Thompson 

Senior Manager, IP and Application Solutions 

October 2007

Agenda 

� Overview Processor Tools 

� CoreConsole 

� Libero 

� SoftConsole 

� Porting code from ARM7 to Cortex-M1 

� DEMO – Build a Cortex-M1 System 

Confidential 

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Cortex-M1 - Next Member of the M Series 

� Designed for FPGA Implementation 

� Soft Processor (Implemented in FPGA Fabric) 

� Small, Powerful, Highly-optimized for FPGAs 

� Configurable 

� ARMv6-M Architecture 

� Subset of Thumb-2 

� All 16-bit Thumb Instructions and some 32-bit Instructions 

� Delivered as Black Box via CoreConsole 

� Highly secure 

� Users can connect IP to processor 

� Fully implemented in fabric 

� User can program into device 

Confidential 

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Actel Cortex-M1 Design Flow 

HARDWARE 

DEVELOPMENT FLOW 

CoreConsole 

CoreConsole 

• Select Processor 

• Choose Peripherals 

• Add Optional User Custom IP 

• Auto Stitch to to Build System 

Libero IDE 

• Combine System with 

Non Non-Processor on-Processor Processor Code 

• Synthesis, Simulation, and 

Layout 

• Optional Timing/Power 

Analysis 

• Easy to to use GUI 

SoftConsole 

SoftConsole 

• Eclipse-Base Eclipse Base IDE 

• GNU C-Compiler 

C Compiler 

• GNU Debugger 

• Memory Map and Peripheral 

Core Driver File Import 

Confidential 

SOFTWARE DEVELOPMENT FLOW 

OR 

Industry Standard Support 

• Compilers – RealView, Keil, IAR, GNU 

• RTOS – uC/OS uC/OS 

II, uClinux, Nucleus 

• APIs, Drivers – Jungo, Jungo, 

GAO Research 

• Debuggers – RealView, GDB, IAR 

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HARDWARE 


CoreConsole 

CoreConsole 





Libero IDE 




Layout 


Analysis 


SoftConsole 

SoftConsole 



C Compiler 




Confidential 


OR 






GAO Research 


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CoreConsole - HW Development Tools 

� SOC Builder and IP Deployment 

� Fast assembly and configuration of user designs 

� Easy-to-use graphical user interface 

� Wide range of AMBA peripheral IP 

� CoreConsole v1.3 

� Can be downloaded from www.actel.com 

� System output as configured RTL 

� Allows easy system setup and configuration 

� Cortex-M1 output as a blackbox 

� Full support for Cortex-M1 

� Seamless integration with Libero IDE 

Confidential 

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System-on-Chip - Cortex-M1 

� Processor System 

� Processor 

� Bus Fabric 

� Components 

� Components 

� Cortex-M1 

� AMBA 

� IP Cores 

� CoreConsole 

Automatically 

Creates Basic 

System 

� …OR …User Can 

Create System 

Manually 

Confidential 

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IP Cores Available in CoreConsole 

� Processors 

� Cortex-M1, CoreMP7 

� Core8051s, CoreABC 

� AMBA Interfaces 

� CoreAHB, CoreAHBLite 

� CoreAPB, CoreAPB3 

� CoreAHB2APB 

� Other Interfaces 

� Core10/100, Core429, 

CorePCIF 

� Core1553BRT, Core1553BRM 

� Subsystem Cores 

� CoreAHBNvm 

� CoreAHBSram 

� CoreAI 

� CoreCFI 

� CoreDDR 

� CoreFMEE 

� CoreFROM 

� CoreGPIO 

� CoreI2C 

� CoreInterrupt 

� CoreMemCtrl 

� CorePWM 

� CoreRemap 

� CoreSDR 

� CoreSMBus 

� CoreTimer 

� CoreUART, CoreUARTapb 

� CoreWatchdog 

Confidential 

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Building an SoC with CoreConsole 

� Decide on components needed to meet system 

requirements. 

� Add busses and bridge as necessary 

� Add components 

� Connect to busses 

� Configure components and memory map placement. 

� Generate system 

� Test and Verify the system 

Confidential 

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Cortex-M1 - CoreConsole Configuration 

� Select Debug Interface 

� None (Default) 

� RealView JTAG 

� FlashPro3 

� Select Die 

� M1AFS600 (Default) 

� M1A3P1000 

� Future Project-Wide Setting 

� Other Options Inactive 

Confidential 

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Stitching an SOC Together 

� CoreConsole enables components to be stitched to 

the AHB and APB busses 

� Components ‘advertise’ the interfaces they have 

available 

� Auto-Stitching supported 

to accelerate this task 

� User can add and remove 

individual connections 

� Ad-Hoc connections are 

selected from drop down 

configuration boxes 

Confidential 

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Adhoc Signal Connections 

� To connect 

� Right Click on component and click 

configure 

� Or click 

� Label the connection 

� Select ‘From’ component and pin 

� Select ‘To’ component 

and pin 

� Click connect 

� Observe the connection label added 

to schematic 

Confidential 

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Rapid SOC Generation 

� Items to be Generated are Selected in 

This Tab 

� Output Folder Tree is 

C:\CoreConsole\LiberoExport\ 

� Details of the Files Output are 

Communicated to Libero in an XML File 

� Libero uses this to import a design 

� All the Files Generated by 

CoreConsole Can Be Located on the 

Disk And Manually Edited 

Confidential 

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HARDWARE 


CoreConsole 

CoreConsole 





Libero IDE 




Layout 


Analysis 


SoftConsole 

SoftConsole 



C Compiler 




Confidential 


OR 






GAO Research 


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Libero IDE 

� Libero Project Manager 

� Manages design flow and files 

� Design Creation/Verification 

� HDL, SmartGen Cores, Schematic 

� Optimization 

� Test Bench 

� Verification 

� Design Implementation 

� Floor planning & physical constraints 

� Place & Route 

� Timing constraints & analysis 

� Power analysis 

� Program file generation 

� Programming and Debug 

� FlashPro3 supports Programming for all 

Fusion devices 

Confidential 

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Libero IDE 

Design 

Hierarchy 

View 

Catalog: 

- Configurable Cores 

- HDL Templates 

-Macros 

- Bus Interfaces 

Confidential 

Design Entry Tools 

Interactive 

Design Flow 

Management Tools 

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Log File 

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Libero IDE - Project Manager 

File 

Manager 

View 

Catalog: 

- HDL Templates 

- Simple click to 

insert into HDL 

code 

- Proven/tested 

Confidential 

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Libero IDE Design Entry 

Designer Block Flow 

� Create Fully Optimized Functional 

Blocks Through Layout 

� Preserves placement and timing 

� Publish to design repository 

� Supports Design & Re-use goals 

� Published Block Fully Compatible with 

Libero Design Flow 

� SmartDesign 

� Traditional 

Design Entry Options 

� CoreConsole Processor Subsystems 

� CoreConsole Configured Direct Cores 

� User Created HDL Modules 

� Libero Created “Designer Blocks” 

� ViewDraw Schematic 

� Mixed HDL Designs 

� Mixed Schematic/HDL Designs 

� SmartGen Configured Cores 

� Partner Created Companion Cores 

� SmartDesign Components/Modules 

Confidential 

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Synthesize with Synplicity’s Synplify AE 

� Synplify AE 

� Leading edge 

synthesis from the 

market leader 

� Close OEM 

partnership provides 

optimal benefit to 

Actel users 

� Integration with 

Libero IDE ensures 

seamless operation 

� Optimized 

performance and 

area utilization for 

all Actel FPGAs 

� Available in Free 

Libero Gold 

Confidential 

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Mentor Graphics ModelSim HDL Simulator 

� HDL simulation in VHDL or Verilog 

� Pre-synthesis simulation 

� Post-synthesis simulation 

� Post-layout simulation 

Simulate 

Confidential 

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Libero IDE - Designer User Interface 

Physical 

Implementation 

Tools 

Constraint & 

Analysis Tools 

Log & Device 

Information 

Confidential 

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Libero IDE- “Designer” Physical Implementation 

� Designer Functions 

� Import Netlist, Compile, and Design Rule Check 

� Floor planning and physical constraints 

� Timing driven Place and Route 

� Back annotated timing for full timing simulation 

� SmartTime setup of Timing Constraints and Timing Analysis 

� SmartPower analysis of power consumption 

� Generate bitstream or STAPL programming files 

� Comprehensive log file and reports 

Confidential 

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Libero IDE - SmartTime Timing Constraints 

� Visual Dialogs simplify constraint entry 

� View scope of timing paths 

� Select ports 

� Set Clock Edge 

� Enter Timing Requirements 

Confidential 

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Libero IDE - Program File Generation 

� Program File Generation for ProASIC3/E 

� Program 

� Security Settings 

� Security Level 

� Pass Key 

� AES Key 

� FPGA Array 

� FlashROM 

Confidential 

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Device Programming and Debug 

� Programming Software 

� FlashPro 

� In System Programming (ISP) for Actel Flash devices 

� Supports all FlashPro hardware programmers 

� Includes ChainBuilder 

� Generates a merged STAPL file for programming Actel 

FLASH devices in a mixed IC environment 

� Silicon Sculptor 

� Supports all Actel devices 

� Use with Silicon Sculptor hardware programmers 

� Launch from Libero Project Manager or stand alone 

� Device Debugging 

� Synplicity Identify Debugger 

Confidential 

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HARDWARE 


CoreConsole 

CoreConsole 





Libero IDE 




Layout 


Analysis 


SoftConsole 

SoftConsole 



C Compiler 




Confidential 


OR 






GAO Research 


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SoftConsole - Processor SW Development 

� Software development environment 

� Eclipse-based IDE - easy user interface 

� Supports Cortex-M1, CoreMP7, Core8051/s 

� Can be downloaded from www.actel.com 

� C/C++ programming and debug 

� CodeSourcery G++ ARM tools 

� SDCC 8051 compiler 

� Programming and debug with 

Actel’s FlashPro3 

� Can import existing code 

� Open platform for application development 

� Support for RTOS and stacks 

� uC/OC, uClinux 

� TCP/IP, USB, IPMI 

Confidential 

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SoftConsole GNU C/C++ Compiler 

� Extensive intelligent ARM optimization 

� Built from CodeSourcery G++ GNU/GDB 

� Includes many features useful for embedded systems 

� Powerful inline assembly syntax 

� Comprehensive linker script language permitting exact placement of 

code and data 

� Large developer base results in tool stability 

� ISO C and C++ language support 

� Complete runtime libraries 

� Aggressive code usage analysis and syntax warnings 

� Supports ARM EABI for better portability 

Confidential 

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SoftConsole GDB Debugger 

� Support for source- and assembly-level debugging 

� Live debugging of new code 

� In an FPGA or in the GDB ARM simulator 

� Breakpoints can occur when certain conditions are met 

� Intelligent access to hardware 

� Register banks and memory ranges 

� Hover over a variable to read its current value 

� Changes in value are obvious for any variable, memory or register 

� Current stack frame displayed while debugging 

� Evaluation of expressions at runtime 

Confidential 

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On-Chip Debugging via FlashPro3 

� Download and debug executable programs to 

development boards using FlashPro3 

� Can program and debug processor memory and FPGA fabric with 

FlashPro3 

� Reduces pin-count – Utilizes dedicated FPGA JTAG pins via 

UJTAG versus GPIO RVI-ME configuration (10-pins) 

� Full debugging of code on remote target 

� View internal registers, memory locations, variables, etc. 

� Uses the same interface as 

Instruction Set Simulator 

� Only one tool to learn 

Confidential 

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Porting software from ARM7 to Cortex-M1 

� Cortex M Processors More User-friendly than ARM7 

� Less Need for Assembler Code 

� Main Differences from Software Porting Perspective: 

Feature 

Execution State 

Memory Map 

Interrupts 

System Status 

Cortex-M1 

Thumb-2 Only 

Structured (Architecturedefined) 

Integrated NVIC, up to 32 

Interrupts 

xPSR (Stacked Registers) 

Confidential 

CoreMP7 

ARM or Thumb 

Unstructured 

IRQ and FIQ Inputs 

External Interrupt Controller 

PSR (Banked Registers) 

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ARM7TDMI overview 

� 32/16-bit RISC Architecture (ARM v4T - Thumb) 

� 32-bit ARM Instruction Set 

� 16-bit Thumb Instruction Set 

� 32-bit ALU 

� 3-stage Pipeline 

� Unified 32-bit Bus Interface 

� Fully-static Operation 

� Extensive Debug Facilities 

� Embedded Real-time Debugging Block 

� JTAG Interface 

� Support for Trace 

Confidential 

TDMI Stands for: 

� Thumb 

� Debug Support 

� Multiplier (64-bit Result) 

� In-Circuit Emulator Interface 

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Cortex-M1 vs. ARM7 


Smaller 2/3 Size, 2.5 x Faster 

4435 Tiles, 69.9 MHz without Debug 

New Processor 

Designed Specifically for FPGA 

Implementation 

Sophisticated Interrupt Support 

1 – 32 Interrupts 

Automatic Processor State Saving and 

Restoration 

Deterministic, Short Interrupt Latency 

4 Levels of Interrupt Priority – Set by User 

ARM7 (CoreMP7) 

Bigger, Slower in FPGAs 

6083 Tiles, 28 MHz without Debug 

Industry-standard Processor 

Well-established and Recognized in ASIC 

Market (around for >15 Years) 

Initially Custom Design (Only Later Made 

Available as Synthesizable RTL 

Simple Interrupt Support (Two Interrupts – 

IRQ and FIQ) 

No Auto State Saving or Restore 

Long, Non-deterministic, Interrupt Latency 

FIQ Has Priority over IRQ – Fixed 

Confidential 

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Cortex-M1 vs. ARM7 (cont.) 


Connects Directly to AMBA 

External Interface is AMBA AHB-Lite 

Separate Memory Interface from AMBA 

1 Clock Cycle per Instruction Access 

Harvard Architecture – Separate Instruction 

and Data Interfaces 

Tightly-coupled Memories (TCM) up to 1MB 

Defined Memory Map 

Only Supports Thumb Instructions (All 16bit 

Thumb Instructions and Some Thumb-2 

32-bit Instructions) 

Does Not Execute ARM Instructions 

ARM7 (CoreMP7) 

External Interface Is Native ARM7 – Not AMBA 

Requires Bridge to AMBA 

Memory Accesses over AMBA 

Each Instruction Access Is at Least Two 

Clock Cycles 

von Neumann Architecture – Shared 

Instruction and Data Interface 

Unstructured Memory Map 

(Exception Vectors from Address 0 Onwards, 

No Further Restrictions) 

Normally Executes ARM Instructions 

Can also Execute 16-bit Thumb Instructions 

but Must Change State to Do This 

Confidential 

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Cortex-M1 - Instruction Set 

� ARMv6-M ISA (Subset of Thumb-2) 

� All 16-bit Thumb Instructions and Some 32-bit Thumb-2 

Instructions 

� Ideal C Compiler Target 

� Reduces Time to Market and Improves Code Quality 

� Interrupt Service Routines Can Be Coded Directly as C 

Functions 

Confidential 

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Cortex-M1 - Registers 

� 17 Registers 

� 13 General-Purpose Registers 

� Stack Pointer 

� Link Register 

� Program Counter 

Cortex-M1 register file is same as ARM7 register file 

Confidential 

Low Registers – 

Accessible by All 

Instructions 

High Registers – 

Accessible by 

SOME 16-bit 

Instructions 

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� Components of Embedded Software System 

� Application Code (Typically C/C++) 

� Should Remain Largely Unchanged 

� May Need Minor Modifications 

� Re-compile Source Code with Cortex-M1 as Target 

Confidential 

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� System Code (C and Assembler Code) 

� Porting System Code – the Crux of the Matter 

� C Code – Modify to Suit Different Resource Locations (e.g., Interrupt 

Controller) and Re-compile, Targeting Cortex-M1 

CoreMP7 (ARM7) 

Assembler Code 

Start-up Code and Vector 

Table 

Exception (Interrupt) 

Handlers 

Access to System Features 

Tips for Porting to Cortex-M1 

Simpler for Cortex-M1 – Vector Table Composed of 

Addresses rather than ARM Instructions 

May Be Possible to Completely Avoid Assembler Code 

for This 

Automatic State Saving and Restoration Makes 

Exception Handling Easier for Cortex-M1 

Exception Handlers May Be Written in C 

e.g., Enabling/Disabling Interrupts 

Must Be Manually Ported 

Confidential 

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HARDWARE 


CoreConsole 

CoreConsole 





Libero IDE 




Layout 


Analysis 


SoftConsole 

SoftConsole 



C Compiler 




Confidential 


OR 






GAO Research 


39 

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Actel M1 Development Boards 

� M1-SYSMGMT-DEV-KIT 

� M1AFS600 device 

� System Mgmt GUI 

� Demonstration designs 

� Full PCI interface 

� Also available with FP3 

� M1 SOC Boards 

� Powered by USB or wall supply 

� 1M SRAM, 4M Flash memory 

� FP3 programmer built into board 

� Expansion connectors 

� M1A3P-DEV-KIT-SCS 

� M1A3P1000 device 

� M1AFS-DEV-KIT-SCS 

� M1AFS600 device 

� M1AGL-DEV-KIT-SCS 

� M1AGL600 device 

Confidential 

M1A3P1000 

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Where to Go for More Information 

� Cortex-M1 on the Web 

� http://www.arm.com/products/CPUs/ARM_Cortex-M1.html 

� http://www.actel.com/products/mpu/CortexM1/ 

� Key Documents 

� Cortex-M1 Handbook (Actel) 

� ARM v6-M Architecture Reference Manual (ARM) 

� Cortex-M1 Technical Reference Manual (ARM) 

� Registration on ARM’s Website Required for Some 

Documents 

Confidential 

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Summary 

� Cortex-M1 allows designers to benefit from 

hassle-free, industry-standard ARM architecture 

� Optimized for use in M1 devices (ProASIC3, IGLOO, Fusion) 

� Actel FPGA tools offer seamless development flow 

� CoreConsole, Libero, dev kit hardware development tools 

� SoftConsole with GNU software development tools 

� Third-party ecosystem support 

� Brings flexibility and fast time to market to system-level 

designs 

Confidential 

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Implementing Hardware and Software for an ARM Cortex-M1 in FPGA

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