Dynamic Shift Registers - Bitsavers - Trailing-Edge

absolute maximum ratingsVGG Supply VoltageVoo Supply VoltageInput VoltageStorage TemperatureOperating Temperature MM4230MM5230Vss-30VVss-15V(Vss -20)V < VI N< (Vss +O.3)V-65°C to +150°C-55°C to +125°C-25°C to +70°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A within operating temperature range, Vss = + 12V ±5% and V GG = -12V ±5%, unless otherwise specified.PARAMETER CONDITION MIN TYPOutput Voltage LevelsMOSto MOSLogical "1"1 Mn to GND Load (Note 1)Logical "0" Vss -1.0MAXVss -9.0UNITSVVMOSto TTLLogical "1"6.8 kn to VGG Plus OneLogical "0" Standard Series 54/74 Gate Input +2.4+0.4 VVInput Voltage LevelsLogical "1"Logical "0" Vss -2.0Vss -8.0VVPower Supply Current TA = 25°CVss 24VGG (Note 1)I nput Leakage V IN = Vss -12VI nput Capacitance f = 1.0 MHz V IN = OV 5Access Time (Notes 2, 3) TA = 25°CT ACCESS (See Timing Diagram) 150 500Vss = +12V VGG = -12V40 mA1 pA1 pApF725 nsOutput AND ConnectionMOS LoadTTL Load38Note 1: The VGG supply may be clocked to reduce device power without affecting access time.Note 2: Address time is measured from the change of data on any input or Chip Enable line to theoutput of a TTL gate. (See Timing Diagram.)Note 3: The access time in the TTL load configuration follows the equation: T ACCESS = thespecified time + (N-1) (50) ns where N = number of AND connections. The number of AND ties inthe MOS load configuration can be increased at the expense of MOS "0" level.88