Dynamic Shift Registers - Bitsavers - Trailing-Edge

illSROMsMM4230/MM5230 2048-bit read only memorygeneral descriptionThe MM4230/MM5230 is a 2048-bit static readonly memory. It is a P-channel enhancement modemonolithic MOS integrated circuit utilizing lowthreshold voltage technology. The device is a nonvolatilememory organized as 256-8 bit words or512-4 bit words. Programming of the memory contentsis accomplished by changing one mask duringthe device fabrication. Customer programs may besupplied in a tape, card, or pattern selection format.features• Bipolar compatibility• High speed operation 500 ns typblock and connection diagrams• Static operation no clocks required• Common data busing output wire ANDcapability• Chip enable output control.applications• Code conversion• Random logic synthesis• Table look-up• Character generators• Micro-programming.• .,un(LSI! A,IE.EAMPL.fllR'GUTI'mI,Dual-In-Line Package..I,....IIUIIORV"...."..eM".. ----~--~ ~+4-------- EI,uLEMODE-COIIIT«OL --------1'--'1"'IN'UTA3INPUT"!INPUT A,OUTPUTB,OUT'UTI2ounUTllout,u,l.OUTPUT 15OUTPUT~OUT'UT8,OUTPUT IsV"I_PUlA.II'UTA1INPUT A..V"".. ..CONTROLCHI'ENAILE1Z INPUT A,TOPVUWtypical application256 x 8 Bit ROM Showing TTL InterfaceOperating Modes-12V+fZV"V-{_toTTL GATESt I,l' CHIPlUlU..t MOO£COlLraUl... .. IIu.- ..I,v .... II.. U...II tov ....II"....I, II .._31tJWm1D.."n I,ItC.v".. I," ""..U.U •"V}-256.8 ROM connectionMode Control - Logic ·'0"A. - Logic "'"5'2.4 ROM connectionMode Control - Logic •• ,,,A. - Logic "0" Enables the odd(B,. 8, ... B.) outputs- Logic ."" Enables the even(B,. B4 ... B.) outputs .The outputs are ··Enabled" when a logic "'" isapplied to the Chip Enable line.The outputs are connected to V DO through aninternal MOS resistor when "Disabled.".".87