Dynamic Shift Registers - Bitsavers - Trailing-Edge

absolute maximum ratingsVGG Supply VoltageVoo Supply VoltageInput VoltageStorage TemperatureOperating Temperature MM4221MM5221Lead Temperature (Soldering, 10 sec)Vss - 20V. Vss - 20V(Vss - 20)V < V 1N < (V SS +0.3)V-65°C to +150°C-55°C to +125°C-25°C to +70°C300°Celectrical characteristicsT A within operating temperature range, Vss = +5V ±5%, VGG = Voo = -12V ±5%, unless otherwise specified.PARAMETER CONDITIONS MIN TYPMAXUNITSOutput Voltage LevelsMOS to TTLLogical "1"6.8 kQ ±5% to V GG Plus OneLogical "0" Standard Series 54/74 Gate +2.4Output Current CapabilityLogical "0" V OUT = 2.4V 2.5+0.4 VVmAInput Voltage LevelsLogical "1"Logical "0" Vss - 2.0Vss - 4.2VVPower Supply Current TA = 25°C100 Vss = +5V 6.5IGG (Note 1) VGG = V DO = -12V12.0 mA1 pAI nput LeakageV 1N = Vss - 12V1 pAInput Capacitance f = 1.0 MHz, V 1N = OV 5V GG Capacitance f = 1.0 MHz, V 1N = OV 15Address Time (Note 2)See Timing DiagramTAccEss TA = 25°C, 700Vss = 5VVGG = Voo = -12VpF25 pF950 nsOutput AND Connections(Note 3)6.8 kQ ±5% to V GG Plus OneStandard Series 54/74 Gate8Note 1: The VGG supply may be clocked to reduce device power without affecting access time.Note 2: Address ti me is measured from the change of data on any i·nput except mode control or ChipEnable line to the output of a TTL gate. (See Timing Diagram). See curves for guaranteed limitover temperature.Note 3: The address time in the TTL load configuration follows the equation:TACCESS = The specified limit + (N -1) (50) nsWhere N = Number of AND connections.84