Dynamic Shift Registers - Bitsavers - Trailing-Edge

absolute maximum ratingsVGG Supply VoltageVss - 20VVoo Supply VoltageVss - 20VInput Voltage(Vss - 20)V < V 1N < (Vss +0.3)VStorage Temperature-65°C to +150°COperating Temperature MM4211-55°C to +125°CMM5211_25°C to +70°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A within operating temperature range, Vss = +5V ±5%, V GG = V DO = -12V ±5%, unless otherwise noted.PARAMETER CONDITIONS MIN TYP MAX UNITSOutput Voltage LevelsMOS to TTLLogical "1" 6.8K ±5% to VGG Plus O[1e +0.4 VLogical "0" Standard Series 54/74 Gate +2.4 VOutput Current CapabilityLogical "0" V OUT = 2.4V 2.5 mAInput Voltage LevelsLogical "1" Vss - 4.2 VLogical "0" Vss - 2.0 VPower Supply Current T A = 25°C100 Vss = +5V 6.5 12.0 mAIGG (Note 1) VGG = V DO = -12V 1 /lAI nput Leakage V 1N = Vss - 12V 1 /lAInput Capacitance f = 1.0 MHz, V 1N = OV 5 pFV GG Capacitance f = 1.0 MHz, V 1N = OV 15 25 pFAddress Time (Note 2)See Timing DiagramT ACCESS TA = 25°C, 700 950 nsVss = 5VVGG = Voo = -12VOutput AND Connection 6.8K ±5% to VGG Plus One 8(Note 3)Standard Series 54/74 GateNote 1: The V GG supply may be clocked to reduce device power without affecting access time.Note 2: Address time is measured from the change of data on any input or Chip Enable line to theoutput of a TTL gate. (See Timing Diagram.) See curves for guaranteed limit over temperature.Note 3: The address time in the TTL load configuration follows the equation:T ACCESS = The specified limit + (N -1) (50) nsWhere N = Number of AND connections.76