Dynamic Shift Registers - Bitsavers - Trailing-Edge

absolute maximum ratingsAll Input or Output Voltages withRespect to V BBPower DissipationOperating Temperature Range MM4203MM5203Storage Temperature RangeLead Temperature (Soldering, 10 sec)+.3 to -20V1W-55°e to 85°e-25°e to 70 0 e-65°C to 125°e300 0 eelectrical characteristicsTA within operating temperature range, Vss ~ +5V ±5%, Voo ~ V LL ~ 12V, ±5% unless otherwise noted.PARAMETERCONDITIONSMINTYPMAXUNITSInput Current, IL 1V IN ~ OV1J..IAOutput Leakage, I LOV OUT ~ OV Output in 3rd State1J..IAPower Supply Current, I DO 1TA ~ 25°C3555mAInput LOW Voltage, V ILVss-4.0VInput HIGH Voltage, V IHVss - 2.0VOutput LOW Voltage, VOL1.6 mA sink.40VOutput HIGH Voltage, VOH100 J..IA source2.4VData Hold Time, T OH(Min Access Time) Figures 1 & 2100nsAccess Time, T ACCT A ~ 25°C Figures 1 & 2.7001J..IsChip Enable Time, T CEFigures 1 & 3500nsChip Disable Time, T CDFigures 1 & 3500nsAllowable Chip Select Delay, tcsFigures 1 & 2Allowable delay in selecting chipafter change of address withoutaffecting access time.100nsInput Capacitance, C INOutput Capacitance, C OUTV IN ~Vss }f~ 1.0 MHzGuaranteed byV OUT ~ Vss design (Note 2)(Chip deselected)881515pFpFoperating characteristics for programming operationsTA = 25°C, Vss ~ OV, Vss ~ +12V ±10% unless otherwise notedPARAMETERCONDITIONSMINTYPMAXUNITSAddress and Data Input LoadCurrent,l L12PV 1N ~ -40V10mAProgram V LL Load Current, I L12PV IN ~ -50V10mAVss Supply Load Current, Iss100J..IAPeak IDD·Supply Load Current, loop (Note 3) V LL ~ V DO ~ V program = -50V750mAInput High Voltage, V 1LP+.3VPulsed Data Input Low Voltage, V IH1P-48Address Input Low Voltage, V 1H2P-48Pulsed Input Low Voltage:-50V LL, V DD, and Program, V 1H3P-40-40-48VVVNote 1: During programming, data is always applied in the 256 x 8 mode, regardless of the logic stateof Ag and mode control.Note 2: Capacitances are not tested on a production basis but are periodically sampled.Note 3: lOOp flows only during program period t¢PWp. Average power supply current lOOp istypically 15 mA at 2% duty cycle.Note 4: Maximum duty cycle of t¢pw should not be greater than 2% of cycle time so that powerdissipation is minimized. To guarantee long term memory retention the program cycle should be reopeated five times with t¢pw ~ 20 ms or the equivalent thereof, i.e. 10 cycles of t¢pw ~ 10 ms.68