Dynamic Shift Registers - Bitsavers - Trailing-Edge

MM4203/MM5203 electrically programmable2048-bit read only memory (pROM)general descriptionThe MM4203/MM5203 is a 2048-bit static readonlymemory which is electrically programmableand uses silicon gate technology to achieve bipolarcompatibility. The device is a non-volatile memoryorganized as a 256-8-bit words or 512-4-bit words.Programming of the memory contents is accomplishedby storing a charge in a cell location byprogramming that location with a 45 volt pulse.Separate output supply lead is provided to reduceinternal power dissipation in the output stage(VLd·features• Field programmable• Bipolar compatibility - +5V. -12V operation• High speed operation - 1 /ls max access timeROMs• Pin compatible with MM5213. MM5231mask programmable ROMs• Static operation - no clocks required• Common data busing (TRI-STATETM output)• "a" quartz lid version erasable with ultra-violetlight• Chip enable output control• 256 x 8 or 512 x 4 organizationapplications• Code conversion• Random logic synthesis• Table look-up• Character generator• Micro-programmings:s:~NoeN........s:s:(J1NoeNblock and connection diagramsDual-In-Line Package1/01 1108A, 1A, ,24 Vll23 VB"A,---,~--..,osCONT---'~ __ "",A, 3B, ,22 PROGRAM21 A4B, 520 A5PROGRAMOUTPUTB, 6B, ,B, BB, 919 A618 A,"'"16 VODB,1015 CONTROLBall14C5Vss 1213 Agtypical applicationsTOPVIEW256 x 8 PROM Showing TTL InterfaceOperating Modes"t MOOECONTROLA, 11 I OHITTLLO~IC, 0,256 x 8 ROM connection (shown!Mode Control - HIGHAS - LOW512 x 4 ROM connectionsMode Control - LOWAg - Logic HLGH enables the odd (81,83.. 87) outputs- Logic LOW enables the even (82,84.. 88) outputsoutputsThe outputs are enabled when a logic LOW is applied tothe Chip Enable line.Mode Control should be "hard wired" to VDD (LOW) orVSS IHIGH).Programming is accomplished in 256 x 8 mode only.Pin 23 is connected to VSS except when programmingwhen it is connected to VBB.Program pin is connected to VSS except when programmingprogram pulse is applied.In the programming mode, data inputs 1-8 are Pins 4-11respectively. Chip Enable should be disabled (HIGH).67