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Dynamic Shift Registers - Bitsavers - Trailing-Edge

Dynamic Shift Registers - Bitsavers - Trailing-Edge

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absolute maximum ratingsVoltage at Any Pin Vss + 0.3V to Vss - 20.0VOperating Ambient Temperature Range-25°C to +70°CStorage Temperature Range-65°C to +150°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A with in operating range, V GG = -12V ± 1 0%, V DO = GND, Vss = 5V ±5%, unless otherwise noted.PARAMETER CONDITIONS MIN TYP MAX UNITSData, Clock Control, and Clock LevelsLogical High Level (V IH ) See I nput Level vs V GG Curve Vss - 2.0 Vss + 0.3 VLogical Low Level (VI L) Vss - 4.2 -VI nput Leakages V IN = -10V, T A = 25°C 0.5 pAAll Other Pins GNDData I nput Capacitance V IN = O.OV, f = 1 MHz 4.5 6.0 pFAll Other Pins GN D (Note 1)Clock & Clock Control Capacitance VIN = O.OV, f = 1 MHz 6.0 8.0 pF(Note 1)Data Output Levels See Figure 1Logical High Level (VOH ) ISOURCE = -0.5 mA 2.4 Vss VLogical Low Level (VOL) ISINK = 1.6 mA 0.15 0.4 VPower Supply Current ¢f = 2.0 MHz, T A = 25°C(IGG + 100 = Iss) IGG Vss = 5V, Voo = GND 7.0 10.0 mA100 VGG=-12V 5.0 8.0 mAClock F requ ency (¢f) See Operating Curves DC 3.0 2.2 MHzClock Pulsewidth (¢pw)See Operating Curves andFigure 1Clock Pulsewidth ¢t,= ¢tf = 10 ns 0.25 10 psClock Transition TimesClock Risetime (¢t,) 500 nsClock Falltime (¢tf) 500 nsClock Control Setup Time (tcs) See Figure 1, ¢t, = ¢tf = 10 ns 0 nsClock Control Hold Time (tch) See Figure 1, ¢t, = ¢tf = 10 ns 0 nsData Input Setup Time (td.) See Figure 1, ¢t, = ¢tf = 10 ns 60 30 nsData Input Hold Time (tdh) See Figure 1, ¢t, = ¢tf = 10 ns 40 20 nsData Output Propagation Delay See Figures 1 & 2,From Clock¢t, = ¢tf = 10 nsDelay to Output High Level (tpdH) 200 300 nsDelay to Output Low Level (tpdd 200 300 nsNote 1: Capacitance is guaranteed by periodic testing.64

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