Dynamic Shift Registers - Bitsavers - Trailing-Edge

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performance characteristicsPower Dissipation vs VDD Power Dissipation vs VGG Power Dissipation vs Temp.I~ 3.0..sI-;'!!;:-~iiiZ ....... ...- ..s-Iiii0Z-' .l"t~ 2.0~"... -7,;"t~ 2.0 I---t----:;;oi"""--+-I-~i5 - --- f. ~iii.-.... Vss = OVi5a: 1.0a: 1.0 -....... =-1--+-1-~VGG = -16V~ Voo = -10V0... V. = -16V f V.=VGGFREQ = 10 kHz~ 3.0 I---t--I--+-I--.-9..161412..s 10I... Za:a::::>'"operationVDO-10 -11 -14VOUT vs Load Current-L/V'/to" ;;;;;;;; ~i--""4K EXTERN~~AO(SlNK)o -1 -2 -3 -4 -5 -6 -7 -8 -9VOUT-16-18V GO2.2N 2.0:z:~>- 1.B..I!'l:::> 1.68~ 1.4:;;:::>:;; 1.2.. x:;; 1.0-55 25TEMPE RATU RE 'cMax. Frequency vs Supply Voltages/V/V/' .."VI> = 0.4" ... !il 1 MHzV¢= 0.3" ... !ill.5 MHz-VI> = 0.2""", !il2.0 MHzVoo = -10VI I II --14 -16 -18 -20VGG & VI> (Volts)125A diagram of a one-bit static register employingtwo clock phases (rI>, ¢») is shown in the schematic.The register requires only one external clock phase(rI» since the second clock (4)) is generated internallyby T 19 and 15K; this configuration simplifiesthe input drive requirements.The basic cell functions as follows. Each bit ofdelay consists of three inverters T 2, T 4, and T 8 inconjunction with three MOS load resistors T 3, T 5,and T 9 followed by three coupling devices T 1, T 6,and T 7' The timing diagram shows the sequence ofoperation. Assume the input is at a logic "1" levelduring tl time. When the cloc!: (rI» goes to a logic"1" level, two operations take place simultaneously.First, transistor TI turns "ON", transferringthe input data (logic "1" level) to the gate tosource capacitance (Cd of T 2. The voltage storedon C 1 is sufficient to turn T 2 "ON" dischargingnode B. With the gate to source capacitance (C2)of T4 discharged, T4 turns "OFF" placing a logic"1" level at node C. Concurrently rI> turns T 19"ON" generating the complement of rI>, that is rI>and in turn 4> is used to turn T 6 and T 7 "OFF".This action allows the register's previous informationto be temporarily stored on the gate to sourcecapacitance C 3 of T 8' The output at node E duringthis timing sequence remains unchanged. However,during t2 time, clock rI> returns to ground;concurrently 4> goes to a logic "1" level turning T 1"OFF" allowing T6 and T7 to turn "ON". Theinformation which was previously stored on thegate of T 8 discharges to a logic "0" level causingthe output at node E to switch to a logic "1" levelthereby obtaining the required one·bit of delay.Likewise the information at node C is fed back tonode A latching T 2 in the "ON" state.When a logic "0" level is presented at the registerinput, the sequence is once again repeated. The bitdelay.demonstrated in this example is repeated foreach half of the dual static register.timing diagramI I "--_--1 II I I I IINPUTDATA~, ~I ('---;'1-1 I,r-'--'-~II~' I ----+1 ~'iI ---
Static <strong>Shift</strong> <strong>Registers</strong>MM4040/MM5040 dual 16-bit static shift registergeneral descriptionThe MM4040/MM5040 dual 16-bit static shiftregister is a monolithic integrated circuit utilizingP channel enhancement mode low threshold technologyto achieve direct bipolar compatibility onthe inputs and outputs. The device requires onlya single phase clock.features• Bipolar compatibility +5, -12V operationNo pull-up or pulldownresistors needed• High frequency operation 2.2 MHz guaranteed• Single phase clockapplications• Static data buffer• Serial memory storage• Printer memory• Telemetry systems and data samplingconnection diagramMetal Can PackageVDDVssTOP VIEWtypical application+5VVeer- --, 4 VssI IL_~_JI 1II 116 ·BIT S.R.16·BITS.R.ANY DTlITTl DEVICE-12VdcANY DTLITTL DEVICE54
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National Semiconductor CorporationM
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IntroductionHere is National's newe
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RAMsMM1101 256-Bit Fully Decoded St
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MOS Selection GuidePRODUCT TYPE NO.
Page 11 and 12: The five basic elements are interco
Page 13 and 14: absolute maximum ratingsVoltage at
Page 15 and 16: timing diagramsSequence of Command
Page 17 and 18: programming of MM5704 (can't)o coun
Page 19 and 20: ......tnG)G)(I)0010:E:E......00..:E
Page 21 and 22: Dynamic Shift Registers~~ MM1402A/M
Page 23 and 24: performance characteristics! 100,.J
Page 25 and 26: «o ....oLC'):E:E.......«.... oo-.
Page 27 and 28: Dynamic Shift Registers.....enoLn:?
Page 29 and 30: performance characteristicsN~ '"> u
Page 33 and 34: logic table (Notes 3,4)MOOEREGISTER
Page 37 and 38: Dynamic Shift RegistersMM4015A/MM50
Page 39 and 40: performance characteristics~~>...zw
Page 41 and 42: .... co0LC):E:E........CO....0~:E:E
Page 43 and 44: Dynamic Shift RegistersMM4017/MM501
Page 45 and 46: perform ance ch a racteristicslOOkN
Page 51 and 52: performance characteristics!ji,:Ii'
Page 53 and 54: absolute maximum ratingsGate Voltag
Page 59 and 60: performance c ha racte risticsac te
Page 61: absolute maximum ratingsDrain Volta
Page 65 and 66: guaranteed performance characterist
Page 69 and 70: Static Shift RegistersMM4052/MM5052
Page 71 and 72: guaranteed performance characterist
Page 76 and 77: MM4203/MM5203 electrically programm
Page 78 and 79: operating characteristics (con'tl f
Page 80 and 81: ROMsMM4210/MM5210 1024-bit read onl
Page 82 and 83: performance characteristicsGuarante
Page 84 and 85: ROMsMM42111MM52111024-bit read only
Page 86 and 87: performance characteristicsPower Su
Page 88 and 89: MM4220/ MM5220 1024-bit read only m
Page 92 and 93: ROMsMM42211MM52211024-bit read only
Page 94 and 95: performance characteristicsPower Su
Page 96 and 97: illSROMsMM4230/MM5230 2048-bit read
Page 100 and 101: ~12V-----_""' _____________ROMsMM42
Page 104 and 105: ROMsMM4232/MM5232 4096 -bit static
Page 108 and 109: ROMsMM4240/MM5240 2560-bit static c
Page 110 and 111: performance characteristics1200Guar
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ROMsMM42411MM5241 3072-bit static r
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performance characteristicsTypical
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RAMsMM1101/MM11011/MM1101A/MM1101A1
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performance curves (MM1101A/MM1101A
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RAMsMM1103 1024-bit fully decodeddy
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ac operating characteristics (con't
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absolute maximum ratingsAll I nput
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MH0007/MH0007C dc coupled MOS clock
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Clock DriversMH0009/MH0009C dc coup
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MH0012/MH0012C high speed MOS clock
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MH0013/MH0013C two phase MOS clock
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typical performance (cont.)FIGURE 4
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MH0025/MH0025C two phase MOS clock
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applications informationCircuit Ope
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absolute maximum ratings (Notes 1 &
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typical applicationsIfOP~T"IfOPUT"D
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application information (con't)The
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application information (con't)For
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absolute maximum ratingsContinuous
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ininin::?i::?iabsolute maximum rati
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typical input capacitancesMM450, MM
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"litIt)It):?!:?!......."litIt)"lit:
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enQ)...Q)fJ)oCD-o:I:«oIJ')-o:I:«o
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...(I)Q)electrical characteristicse
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absolute maximum ratingsVplus Suppl
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No....~
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Uanor-.M~
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schematic diagramanalog switch data
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(.)0')....ooJ:Z........0')....ooJ:Z
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(.)0')-ooJ:Z........0')-ooJ:Z(.)"d'
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absolute maximum ratingsSupply Volt
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MM482/MM582Voltage Transfer Charact
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ROM Character GeneratorsMM4220N P/M
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ROM Character GeneratorsMM4240ABU/M
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ROM Character GeneratorsMM4240ABZ/M
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ROM Code Convertersrn"owSK0003 sine
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ROM Code Converte rsMM4220AE/MM5220
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ROM Code ConvertersMM4220AP/MM5220A
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ROM Code ConvertersMM4220BL/MM5220B
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ROM Code ConvertersMM4220BM/MM5220B
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ROM Code ConvertersMM4220BN/MM5220B
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MM4220DF/MM5220DF"quick brown fox"
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ROM Code ConvertersMM4220EK/MM5220E
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MM4220LR/MM5220LR BCOIC to ASCII-7/
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ROM Code ConvertersMM4221RO/MM5221R
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ROM Code ConvertersMM4221RR/MM5221R
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11151 ROM Code ConvertersM M 42 30
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code conversion table-selectric-to-
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ROM Code ConvertersMM4230JT /MM5230
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ROM Code ConvertersMM4230KP/MM5230K
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~BlillSROM Code ConvertersMM42300W/
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ROM Code ConvertersMM4230QY/MM5230Q
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ROM Code ConvertersMM4230RS/MM5230R
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A.a:-MNit)~~.......A.a:ROM Code Con
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«coco~r-..:?!c........«coco~Ln:?!
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«0000~.....~c.......«0000~Ln~Ctru
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ROM Code ConvertersDM7598AA/DM8598A
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Custom MOS/LSIo...ct/)o3s:o(J).....
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All designs are verified with a cir
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BriefsJANUARY 1970...aTRIG FUNCTION
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MASK PROGRAMMING SPECIALIZESMOS SHI
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ORDERING INFORMATIONWhen ordering,
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Clock Repetition Rate: The range of
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National Semiconductor Corporation2
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Dynamic Shift Registers - Bitsavers - Trailing-Edge

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