Dynamic Shift Registers - Bitsavers - Trailing-Edge

performance characteristicsPower Dissipation vs VDD Power Dissipation vs VGG Power Dissipation vs Temp.I~ 3.0..sI-;'!!;:-~iiiZ ....... ...- ..s-I­iii0Z-' .l"t~ 2.0~"... -7,;"t~ 2.0 I---t----:;;oi"""--+-I-~i5 - --- f. ~iii.-.... Vss = OVi5a: 1.0a: 1.0 -....... =-1--+-1-~VGG = -16V~ Voo = -10V0... V. = -16V f V.=VGGFREQ = 10 kHz~ 3.0 I---t--I--+-I--.-9..161412..s 10I­... Za:a::::>'"operationVDO-10 -11 -14VOUT vs Load Current-L/V'/to" ;;;;;;;; ~i--""4K EXTERN~~AO(SlNK)o -1 -2 -3 -4 -5 -6 -7 -8 -9VOUT-16-18V GO2.2N 2.0:z:~>- 1.B..I!'l:::> 1.68~ 1.4:;;:::>:;; 1.2.. x:;; 1.0-55 25TEMPE RATU RE 'cMax. Frequency vs Supply Voltages/V/V/' .."VI> = 0.4" ... !il 1 MHzV¢= 0.3" ... !ill.5 MHz-VI> = 0.2""", !il2.0 MHzVoo = -10VI I II --14 -16 -18 -20VGG & VI> (Volts)125A diagram of a one-bit static register employingtwo clock phases (rI>, ¢») is shown in the schematic.The register requires only one external clock phase(rI» since the second clock (4)) is generated internallyby T 19 and 15K; this configuration simplifiesthe input drive requirements.The basic cell functions as follows. Each bit ofdelay consists of three inverters T 2, T 4, and T 8 inconjunction with three MOS load resistors T 3, T 5,and T 9 followed by three coupling devices T 1, T 6,and T 7' The timing diagram shows the sequence ofoperation. Assume the input is at a logic "1" levelduring tl time. When the cloc!: (rI» goes to a logic"1" level, two operations take place simultaneously.First, transistor TI turns "ON", transferringthe input data (logic "1" level) to the gate tosource capacitance (Cd of T 2. The voltage storedon C 1 is sufficient to turn T 2 "ON" dischargingnode B. With the gate to source capacitance (C2)of T4 discharged, T4 turns "OFF" placing a logic"1" level at node C. Concurrently rI> turns T 19"ON" generating the complement of rI>, that is rI>and in turn 4> is used to turn T 6 and T 7 "OFF".This action allows the register's previous informationto be temporarily stored on the gate to sourcecapacitance C 3 of T 8' The output at node E duringthis timing sequence remains unchanged. However,during t2 time, clock rI> returns to ground;concurrently 4> goes to a logic "1" level turning T 1"OFF" allowing T6 and T7 to turn "ON". Theinformation which was previously stored on thegate of T 8 discharges to a logic "0" level causingthe output at node E to switch to a logic "1" levelthereby obtaining the required one·bit of delay.Likewise the information at node C is fed back tonode A latching T 2 in the "ON" state.When a logic "0" level is presented at the registerinput, the sequence is once again repeated. The bitdelay.demonstrated in this example is repeated foreach half of the dual static register.timing diagramI I "--_--1 II I I I IINPUTDATA~, ~I ('---;'1-1 I,r-'--'-~II~' I ----+1 ~'iI ---