Dynamic Shift Registers - Bitsavers - Trailing-Edge

Static Shift Registers*M M404/M M S04 dual16 bit static register*MM40S/MMSOS dual 32 bit static registergeneral descriptionThe National Semiconductor line of MOS staticshift registers are monolithic integrated circuitsutilizing P-channel enhancement mode transistors_The use of a low threshold technology Permitsoperation with a V DD supply voltage of -10 voltsand a V GG supply and clock amplitude voltage ofless than -16 volts. These registers require only asingle clock input to operate from DC to 1 MHzin either synchronous or asynchronous systems.Each register cell is designed specifically to avoidrace conditions during latching, thus insuringoperation under all conditions specified in theelectrical characteristics.Additional features include:• Bipolar compatibility• Single phase clock input• High frequency operation1.0 MHz• Low power consumption 1.7 mW/bit typ• Output impedancl3 (V OH )500Q typ• Military and commercial temperature rangesMM404 MM405 _55°C to +125°CMM504: MM505 -25°C to +70°C~~~oc.n........~~c.noc.nschematic and connection diagrams20KIII15K I,'2,6DATA'OUTPUTVDD,I,cLoci'+'---l'-----.::....-----+-..... ---------~¢ IVaNot.: Pin 4 connecttd to CI.Top Viewtypical applicationsTTL/MOS Interface- -+lDVr-T~I 3'3. V" r-1-1I ~I~~~ I-~ __ ~I~ IIw NA BIT REGISTERI I 1-__ --1I ICLOCK V'h REQUIREMENTS WITH Vss" .,DVlOGIC "0"lOGIC"1"Single 2N Bit RegisterNs BIT REGISTERVssVss -1.5VVss-16V-6VDATA OUTPUT2N Bit Johnson Counter*DrII1 : &:9 IIIII~-------~NOTE: CI'If rllist. to .1 "0" bet .... CGunti,..by .pplyi .. "'" to d .... input .nd dockilllthrough 2N dock cydn.VooGND>il-;~~§~~~=l:t"0IVIOE IBYVo.Waveforms for Applications(complete timing diagrams on page 53),CLOCK ¢ OV ---, r-1 h r-1 r-1 ....-l&V U Lf U U UI....--j.TYPICAL DATA IN -z. 5V ""l I ~\-1.0V~TYPICAL DATA OUT -1.5V "'N"'B"'IT"'O"'EL"'A"'Yo¥---I/ .... """\­.... OV .::....::..:....::=.:......!\;;;;:;-S-.---'_Io.=I2N OUTPUT*For New Designs, see MM4040/MM5040. MM4050A/MM5050A.51