Dynamic Shift Registers - Bitsavers - Trailing-Edge

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absolute maximum ratingsVoltage at Any PinOperating Temperature Range MM4105MM5105Storage Temperature RangeLead Temperature (Soldering. 10 seclVss + 0.3V to Vss - 22V_55°C to +125°C_25°C to +70°C_65°C to +150°C300°Celectrical characteristicsT A within operating temperature range. Vss = +5.0V ±5%. VGG = -12.0V ±10%. unless otherwise specified.PARAMETERCONDITIONSMINTVPMAXUNITSData Input LevelsLogical HIGH Level (V,HILogical LOW Level (V1LIVss - 1.5Vss -18.5Vss + 0.3Vss - 4.2vVData Input Leakage (V,L )V ,N = -20V, T A = 25°C,All Other Pins GND.010.5Data I nput CapacitanceChip Select. Write Control andAddress 2 I nput LevelsLogical HIGH Level (VCH )Logical LOW Level (VcdChip Select, Write Control andAddress 2 I nput LeakageV ,N = O.OV, f = 1 MHz,All Other Pins GNDNote 2V ,N = -20V, T A = 25°C,All Other Pins GNDVss -l.5Vss -18.53.00.15.0Vss + 0.3Vss - 4.21.0pFVVChip Select. Write Control andAddress 2 Input CapacitanceData, Chip Select. Write Controland Address 2 Input Pull·upResistanceV ,N = O.OV, f = 1 MHz,All Other Pins GNDNote 2Vss = 5.0VVGG = -12.0VV ,N = 0.5VTA = 25°C3.0156.0209.0pFClock Input LevelsLogical HIGH Level (V"H)Logical LOW Level (V q,L)Vss - 1.5Vss -18.5Vss + 0.3Vss -14.5VVClock Input LeakageV¢ = -20V, TA = 25°C,All Other Pins GND0.51.0MAClock I nput CapacitanceData Output LevelsLogical HIGH Level (VoHILogical LOW Level (VOL)V¢ = O.OV, f = 1 MHz.All Other Pins GNDNote 2'SOURCE = -0.5 mAISINK = 1.6 rnA2.4100Vss0.4pFVVPower Supply Current IGGClock Frequency (
performance c ha racte risticsac test circuit,..10u;:5 1.0... aII:...u~ 0.1u~!2:iii 0.01-60Guaranteed Minimum ClockFrequency vs Temperature(Note 1)T'N 0' TOUT = MINIMUMV VVT,N = TOUT-20 20 60 100 140AMBIENT TEMPERATURE (OC)100]§ 10li,.::Ii!:::>~ 1.0~0.1Guaranteed Maximum PartialBit Times vs Temperature"-20'"20 60 100 " 140TEMPERATURE (OC)1DPFT"::' ":"timing diagramsFor Writing DataFor Reading Data...CHIPSELECT.RADDRESSDATAOUTPUTExplanation of Timing DiagramsIn order to write·in or read· out of the MM4105/MM5105, the chip select line must be low duringthe appropriate clock cycle. If the chip select line isheld high during the rfJOUT clock pulse the outputwill go high. If it is high during rfJlN time, data maynot be written in. The timing diagram shows thatin order to read from a register all inputs must bestable during rfJlN time. To write information, thewrite control and chip select must be held low.The address lines and data will depend on whatregister is to be selected and what information isto be stored. When the write control line is highthe information stored in the registers is recir·culated.To read information out chip select must be lowand address lines stable during the rfJOUT clock.Information is always recirculated in the fourregisters unless chip select and the write controlare low. Then, depending on which address isselected, only three registers are recirculating whilethe selected register is receiving new data.It is possible to write into and read out of thesame register during one clock period. To writeinformation into the register, chip select and writecontrol are held low during the rfJlN clock. Dataand the address lines must be stable during thesame rfJlN clock. During the next rfJOUT clock time,'chip select is held low with the address unchanged.An output will appear from the same register.To write information into one register and readout of a second register during one clock periodsimilar timing can be used. The address can bechanged between the rfJlN and rfJOUT clocks toselect either of the other three registers.50
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National Semiconductor CorporationM
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IntroductionHere is National's newe
Page 7 and 8: RAMsMM1101 256-Bit Fully Decoded St
Page 9 and 10: MOS Selection GuidePRODUCT TYPE NO.
Page 11 and 12: The five basic elements are interco
Page 13 and 14: absolute maximum ratingsVoltage at
Page 15 and 16: timing diagramsSequence of Command
Page 17 and 18: programming of MM5704 (can't)o coun
Page 19 and 20: ......tnG)G)(I)0010:E:E......00..:E
Page 21 and 22: Dynamic Shift Registers~~ MM1402A/M
Page 23 and 24: performance characteristics! 100,.J
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Page 27 and 28: Dynamic Shift Registers.....enoLn:?
Page 29 and 30: performance characteristicsN~ '"> u
Page 33 and 34: logic table (Notes 3,4)MOOEREGISTER
Page 37 and 38: Dynamic Shift RegistersMM4015A/MM50
Page 39 and 40: performance characteristics~~>...zw
Page 41 and 42: .... co0LC):E:E........CO....0~:E:E
Page 43 and 44: Dynamic Shift RegistersMM4017/MM501
Page 45 and 46: perform ance ch a racteristicslOOkN
Page 49 and 50: Dynamic Shift RegistersMM4020/MM502
Page 51 and 52: performance characteristics!ji,:Ii'
Page 53 and 54: absolute maximum ratingsGate Voltag
Page 57: Dynamic Shift RegistersMM4105/MM510
Page 61 and 62: absolute maximum ratingsDrain Volta
Page 63 and 64: Static Shift RegistersMM4040/MM5040
Page 65 and 66: guaranteed performance characterist
Page 69 and 70: Static Shift RegistersMM4052/MM5052
Page 71 and 72: guaranteed performance characterist
Page 76 and 77: MM4203/MM5203 electrically programm
Page 78 and 79: operating characteristics (con'tl f
Page 80 and 81: ROMsMM4210/MM5210 1024-bit read onl
Page 82 and 83: performance characteristicsGuarante
Page 84 and 85: ROMsMM42111MM52111024-bit read only
Page 86 and 87: performance characteristicsPower Su
Page 88 and 89: MM4220/ MM5220 1024-bit read only m
Page 92 and 93: ROMsMM42211MM52211024-bit read only
Page 94 and 95: performance characteristicsPower Su
Page 96 and 97: illSROMsMM4230/MM5230 2048-bit read
Page 100 and 101: ~12V-----_""' _____________ROMsMM42
Page 104 and 105: ROMsMM4232/MM5232 4096 -bit static
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ROMsMM4240/MM5240 2560-bit static c
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performance characteristics1200Guar
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ROMsMM42411MM5241 3072-bit static r
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performance characteristicsTypical
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RAMsMM1101/MM11011/MM1101A/MM1101A1
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performance curves (MM1101A/MM1101A
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RAMsMM1103 1024-bit fully decodeddy
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ac operating characteristics (con't
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absolute maximum ratingsAll I nput
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MH0007/MH0007C dc coupled MOS clock
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Clock DriversMH0009/MH0009C dc coup
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MH0012/MH0012C high speed MOS clock
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MH0013/MH0013C two phase MOS clock
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typical performance (cont.)FIGURE 4
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MH0025/MH0025C two phase MOS clock
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applications informationCircuit Ope
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absolute maximum ratings (Notes 1 &
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typical applicationsIfOP~T"IfOPUT"D
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application information (con't)The
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application information (con't)For
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absolute maximum ratingsContinuous
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ininin::?i::?iabsolute maximum rati
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typical input capacitancesMM450, MM
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absolute maximum ratingsVplus Suppl
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schematic diagramanalog switch data
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(.)0')-ooJ:Z........0')-ooJ:Z(.)"d'
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absolute maximum ratingsSupply Volt
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MM482/MM582Voltage Transfer Charact
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ROM Character GeneratorsMM4220N P/M
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ROM Character GeneratorsMM4240ABU/M
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ROM Character GeneratorsMM4240ABZ/M
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ROM Code Convertersrn"owSK0003 sine
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ROM Code Converte rsMM4220AE/MM5220
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ROM Code ConvertersMM4220AP/MM5220A
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ROM Code ConvertersMM4220BL/MM5220B
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ROM Code ConvertersMM4220BM/MM5220B
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ROM Code ConvertersMM4220BN/MM5220B
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MM4220DF/MM5220DF"quick brown fox"
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ROM Code ConvertersMM4220EK/MM5220E
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MM4220LR/MM5220LR BCOIC to ASCII-7/
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ROM Code ConvertersMM4221RO/MM5221R
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ROM Code ConvertersMM4221RR/MM5221R
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11151 ROM Code ConvertersM M 42 30
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code conversion table-selectric-to-
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ROM Code ConvertersMM4230JT /MM5230
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ROM Code ConvertersMM4230KP/MM5230K
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~BlillSROM Code ConvertersMM42300W/
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ROM Code ConvertersMM4230QY/MM5230Q
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ROM Code ConvertersMM4230RS/MM5230R
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A.a:-MNit)~~.......A.a:ROM Code Con
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ROM Code ConvertersDM7598AA/DM8598A
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Custom MOS/LSIo...ct/)o3s:o(J).....
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All designs are verified with a cir
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BriefsJANUARY 1970...aTRIG FUNCTION
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MASK PROGRAMMING SPECIALIZESMOS SHI
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ORDERING INFORMATIONWhen ordering,
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Clock Repetition Rate: The range of
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National Semiconductor Corporation2
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