Dynamic Shift Registers - Bitsavers - Trailing-Edge

Dynamic Shift RegistersMM4105/MM5105 quad 64-bitdynamic shift register/accumulatorgeneral descriptionThe MM4105/MM5105 quad 64-bit dynamic shiftregister/accumulator is a monolithic MOS integratedcircu it utilizing P-channel enhancementmode low threshold technology to achieve bipolarcompatability on input/output and control lines.Anyone of four recirculating shift registers maybe selected, by external logic control, for interrogationat the single common output or forwriting in new data at the common input data line.features• TTL compatability+5, -12V power suppliesno pull up or pull downresistors requiredinternal pull upresistors on inputs• Input bus capability chip select allowscontrol of data entryfrom common bus line• Versatile operationapplications• Oata buffers• Disc/drum memory replacement• Register for arithmetic unitsrecirculation and registerselect logic on-chipconnection diagramMetal Can Packagetruth tableLogic Definition"1" Logical HIGH Level"0" Logical LOW LevelCODING AND MODE TABLEAddress Write Control Chip SelectChip1 2 Write Recir Active InactiveSelect· 0 0 0 1 0 1 10 1 0 1 0 1 11 0 0 1 0 1 01 1 0 1 0 1 0Output levelInputOutput0 01 10 11 1typical applicationr-----------------I-----------------.A, B,B,ADDRES52B.NO.2DATA"WRITECONTROLCHIPSEHeTI• IL ________________ ~I~M~-- ______________ ....JNO.36 vCG-12V48