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Dynamic Shift Registers - Bitsavers - Trailing-Edge

Dynamic Shift Registers - Bitsavers - Trailing-Edge

Dynamic Shift Registers - Bitsavers - Trailing-Edge

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absolute maximum ratingsGate Voltage (V G G )Drain Voltage (V D D)Clock Input Voltage (VIP)Data Input Voltage (V IN )Storage TemperatureOperating TemperatureOutput Stress (Parallel Output Lines)- 25V to +O.3V-25V to +O.3V- 25V to +O.3V- 25V to +O.3V-55°C to +125°C-25°C to +70°C-100V (see stress test)electrical characteristics (-25°C to +70°C) (Vss = OV)SYMBOL PARAMETER MIN MAX UNITS CONDITIONV OH Parallel Output Voltage 5 VVGG = Voo Supply Voltage -20.0 -16.0 VIGG Supply Current 6.0 mA Voo = VGG= -20.0V registerloaded alllogical highSerial Inputlevels. Vss = GNDV ,H Logical HIGH Level Vss - 2.5 Vss VV,L Logical LOW Level VGG Vss - 7.0 Vtd• Data Setup Time 400 nstdh Data Hold Time 50 nsSerial OutputVOH Logical HIGH Level Vss - 1.5 Vss VVOL Logical LOW Level VGG Vss - 8.0· VClock AmplitudeV¢H Logical HIGH Level Vss -1.5 Vss VV¢L Logical LOW Level Vss - 20 Vss - 16 VI L Clock Leakage Current 5 pA V¢= -20.0V

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