Dynamic Shift Registers - Bitsavers - Trailing-Edge

absolute maximum ratingsVoltage at Any PinOperating Temperature Range MM4018MM5018Storage Temperature RangeLead Temperature (Soldering, ~O sec)Vss + O.3V to Vss - 22.0V_55°C to +125°C_25°C to +70°C-65°C to +150°C300°Celectrical characteristics(T A within operating temperature range, Vss; +5.0V ±5% and VGG ; -12.0V ±10%, unless otherwise specified.)PARAMETER CONDITIONS MIN TYP MAXData Input LevelsLogical High Level (V,H ) Vss - 2.0 Vss + 0.3Logical Low Level (V,L ) Vss - 18.5 Vss - 4.2Data Input Leakage V ,N ; -20V, T A; 25°C, 0.01 0.5All other pins GNDData Input Capacitance V ,N ; O.OV, f; 1 MHz, 3.0 5.0All other pins GNDClock Input LevelsLogical High Level (V¢H) Vss - 1.5 Vss + 0.3Logical Low Level (V¢L) Vss - 18.5 Vss - 14.5Clock Input Leakage V, ; -20V, T A; 25°C, 0.05 1.0All other pins GNDClock I nput Capacitance V, ; O.OV, f; 1 MHz, 45 60All other pins GNDData Output LevelsLogical High Level (VOH ) ISOURCE ; -0.5 mA 2.4 VssLogical Low Level (VOL) ,SINK ; 1.6 mA 0.4UNITSVVMApFVVMApFVVPower Supply Current (IGG)T A ; 25°C, VGG ; -12V,¢pw; 0.15Ms, V¢L; -12V0.01 MHz::; ¢t::; 0.1 MHz 2.9 4.5¢t;lMHz 3.8 5.5¢t; 2.5 MHz 5.8 7.0mAmAmAClock Frequency (¢t) ¢tr ; ¢tt ; 20 ns (Note 1) 0.01 3.3 2.5Clock Pulsewidth (¢pw) ¢tt + ¢pw + ¢tr ::; 10.5 MS 0.15 10Clock Phase Delay Times (¢d or ¢d) Note 1 10Clock Transition TimesRisetime (¢tr) ¢tt + ¢pw + ¢tr::; 10.5 MS 2Falltime (¢tt! ¢tt + ¢pw + ¢tr ::; 10.5 MS 2Partial Bit TimesInput Partial Bit Time (T,N) Note 1 0.20 100Output Partial Bit Time (TOUT) 0.20 100Data Input Setup Time (tds) 80 30Data Input Hold Time (tdh) 20 0Data Output PropagationDelay from ¢OUTSee AC Test CircuitDelay to Output High Level (t pdH ) 150 200Delay to Output Low Level (tpdLl 150 200MHzMSnsMSMMSMSnsnsnsnsNote 1: Minimum clock frequency is a function of temperature and partial bit times (T, N and TOUT)as shown by the ¢t versus temperature and T,N, TOUT versus temperature curves. The lowest glJaranteedclock frequency for any temperature can be attained by making T, N equal to TOUT' The1minimum guaranteed clock frequency: q)f(min) ; T T ' where T,N and TOUT do notexceed the guaranteed maximums. IN + OUT38