Dynamic Shift Registers - Bitsavers - Trailing-Edge

.... co0LC):E:E........CO....0~:E:Eabsolute maximum ratingsVoltage at Any Pin Vss + 0.3V to Vss -22VOperating Temperature Range MM4016 -55°C to +125°CMM5016-25°C to +70°CStorage Temperature Range-65°C to +150°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A within operating temperature range, Vss = +5.0V ±5%, V GG = -12.0V ±10%, unless otherwise specified.PARAMETER CONDITIONS MIN TYP MAXUNITSData I nput LevelsLogical HIGH Level (V IH ) Vss - 2.0 Vss + 0.3Logical LOW Level (VIL) Vss - 18.5 Vss - 4.2Data Input Leakage V IN = - 20V, T A = 25°C, 0.01 0.5All Other Pins GNDData I nput CapacitanceV IN = O.OV, f = 1 MHz,All Other Pins GND, (Note 2) 3.0 5.0Clock I nput LevelsLogical HIGH Level (V¢H) Vss - 1.5 Vss + 0.3Logical LOW Level (V¢d Vss - 18.5 Vss - 14.5Clock Input Leakage VrfJ = -20V, T A = 25°C, 0.05 1.0All Other Pins GNDClock Input Capacitance VrfJ = O.OV, f = 1 MHz, 100 120All Other Pins GND, (Note 2)Data Output LevelsLogical HIGH Level (VOH ) ISOURCE = -0.5 mA 2.4 VssLogical LOW Level (VOL) ISINK = 1.6 mA 0.4Power Supply CurrentIGGTA = 25°C, VGG = -12V,rfJpw = 150 nsVss = 5.0V, VrfJL = -12V,Data = 0-1-0-10.01 MHz:S: rfJf:S: 0.1 MHz 1.0 2.0rfJf = 1 MHz 3.5 5.0rfJf = 2.5 MHz 7.0 10.0Clock Frequency (rfJf) rfJt, = rfJtf = 20 ns, (Note 1) 0.01 3.3 2.5Clock Pulsewidth (rfJpw) tf = rfJpw + rfJt,:S: 10.511s 0.15 10Clock Phase Delay Times (rfJd, ¢d) (Note 1) 10Clock Transition Times (t" rfJtf) rfJtf + rfJpw + rfJt, :s: 10.511s 1Partial Bit Times (T) (Note 1)Input Partial Bit Time (TIN) 0.20 100Output Partial Bit Time (TOUT) 0.20 100Data Input Setup Time (td,) 80 30Data I nput Hold Time (tdh) 20 0Data Output Propagation DelaySee ac test circuit.from ouTDelay to HIGH Level (tpdH) 150 200Delay to LOW Level (tpdL) 150 200VVI1ApFVVI1ApFVVmAmAmAMHzI1snsI1sI1sI1snsnsnsnsNote 1: Minimum clock frequency is a function of temperature and partial bit times, TI N and TOUT,as shown by the t/>f versus temperature and TIN, TOUT versus temperature curves. The lowest guaranteedclock frequency for any temperature can be attained by making TIN equal to TOUT. The1minimum guaranteed clock frequency is: t/>f(min) =,where TIN and TOUT may notTIN + TOUTexceed the guaranteed maximums.Note 2: Capacitance is guaranteed by statistical lot sample testing.32