Dynamic Shift Registers - Bitsavers - Trailing-Edge

Dynamic Shift RegistersMM4015A/MM5015A triple 60+4 bit accumulator/registergeneral descriptionThe MM4015A/MM5015A triple 60+4 bit dynamicaccumulator is a monolithic MOS integrated circuitutilizing P-channel enhancement mode lowthreshold technology. The device consists of threeindependent shift registers with logic to controlthe entry of external data or to recircu late thedata stored in that register. A common two phaseclock is requ ired to operate the device.• Low frequency operation• Low power consumption• Recirculate logic on-chip• BCD correction look ahead tapapplications250 Hz at 25°Cguaranteed0.4 mW/bittypically at 1 MHzfeatures• Data storage registers in BCD arithmetic appl i-• Direct DTL and TTL compatibility No p.ull-upcationsor pull-down • Basic accumulator functionsresistors required • Business machine memory applications• High frequency operation 2.5 MHz guaranteed • Recirculating delay lineconnection diagramDual-I n-Line PackageINPUT! 1 16 VOGLOAOCONTROll 2~-1f--15 OUTPUT IAOUTPUTIB J-+---+-=-------'INPUT 2 4 -I-----f",14 OUTPUT2AlJOUTPUT3ALOAD CONTROl2 5OUTPUl2B 6INPUTJ 1~:>-E:;~+-J;;h--.~ to OUTPUTlBVss 8L'=========="-_~_g LOAD CONTROLJNote Pili 8 conneGted to case.TOPVIEWtypical applicationsTTL/MOS Interface~~, r------I.------, r-I~,r TTl/Dn MM4015AIMM5D15A TTl/OTlI I " I ITypical Arithmetic ConfigurationtOld Cont.ol : ~::: ~~; = ~:::: ~::~.:~.~.A+C ___ S-,A-_A28