Dynamic Shift Registers - Bitsavers - Trailing-Edge

absolute maximum ratingsVoltage at Any Pin Vss + 0.3 to Vss - 22Operating Temperature Range MM4013-S5°C to +12SoCMMS013- 2SoC to +70°CStorage Temperature Range-6SoC to +lS0°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A within operating temperature range, Vss = +5.0V ±5%, V GG = -12.0V ± 10%, unless otherwise noted.PARAMETER CONDITIONS MINData I nput LevelsLogical HIGH Level (V'H) Vss - 2.0Logical LOW Level (V,e!Vss -18.SData I nput LeakageV ,N ' -20.0V, TA • 2SoC,All Other Pins GNDData I nput CapacitanceY'N • O.OV, f· 1 MHz,All Other Pins GNDControl Input Levels(Note 1)Logical HIGH Level (VHI Vss - 2.0Logical LOW Level (Ve! Vss - 18.5Control Input LeakageY'N • -20.0V, T A • 25°C,All Other Pins GNDControl Input CapacitanceV ,N • O.OV, f· 1 MHz,All Other Pins GNDClock I nput LevelsINote 11Logical HIGH Level (V.H )Vss - I.SLogical LOW Level (V.e! Vss - 18.5Clock Input LeakageV.' -20.0V, TA • 25°C,All Other Pins GNDClock I nput CapacitanceV.' O.OV, f· 1 MHzAll Other Pins GNDData Output Levels(Note 11Logical HIGH Level (VoHI 'SOURCE = -0.5 rnA 2.4Logical LOW Level (Voe!'SINK = 1.6 rnAData Output Leakage VOUT ' -5.0V, T A • 25°COutput in Highlmpedance StatePower Supply CurrentIGGTA = 25°C, VGG ' -12V,¢pw' ISO ns, Vss' 5.0V,V.L • -12V, Data' 0-1-0-10.01 MHz:'O: 41,:'0: 0.1 MHz41, • 1.0 MHz41,' 2.5 MHzClock Frequency (41,1 ¢t,' ¢t,' 20 ns, (Note 21 0.01Clock Pulsewidth (¢pwi ¢t, + ¢pw + ¢t,:'O: 10.5 j.lS 0.15Clock Phase Delay Times (¢d, iFd) (Note 2) 10.0Clock Transition Times (¢t,. ¢tf)¢t, + ¢pw + ¢t,:'O: 10.5 j.lsPartial Bit Times (T) (Note 21Input Partial Bit Time (TIN) 0.2Output Partial Bit Time (TOUT) 0.2Data Input Setup Time (tds) 80Data Input Hold Time (tdh) 20Write Setup Time (!OUTDelay to HIGH Level (tpd')Delay to LOW Level (tpdo)Propagation Delay FromRead Control Disable toHIGH Impedance State:Delay From HIGH level (t1H)Delay From LOW Level (toHIPropagation Delay FromRead Control Enable toLOW Impedance State:Delay to HIGH Level (tH')Delay to LOW Level (tHO)(see ac test circuit)TYP1400.D13.00.013.00.051.605.310.3303.30300150150150ISO150150MAXUNITSVss + 0.3VVss - 4.2V0.5 j.lA5.0 pFVss + 0.3VVss - 4.2V0.5 j.lA5.0 pFVss + 0.3VVss - 14.5V1.0 j.lA160 pFVssV0.4 V10.0 j.lA3.0 mA8.0 mA15.0 mA2.5 MHz10 j.lSns1.0 j.ls100 j.lS100 j.lSnsnsnsnsnsns200 ns200 ns200 ns200 ns200 ns200 nsNote 1: Capacitance is guaranteed by periodic testing.Note 2: Minimum clock frequency is a function of temperature and partial bit times (TIN and TOUT)as shown by the 1>t versus temperature and TIN, TOUT versus temperature curves. The lowest guar·anteed clock frequency for any temperature can be attained by making TIN equal to TOUT' Theminimum guaranteed clock frequency:1¢tlmin) '= TIN + TOUT where TIN and TOUT do not exceed the guaranteed maximums.Note 3: Minimum clock frequency and partial bit time curves are guaranteed by testing at a hightemperature point.26