Dynamic Shift Registers - Bitsavers - Trailing-Edge

logic table (Notes 3,4)MOOEREGISTERSELECTCONTROLENABLECONTROLSFUNCTIONPIN 9PIN 10 PIN 11INPUTSELECTIONI0I0001oooA Register to A input, 8 Register to B inputA Register to A input, B Register to B inputA Register to A input, B Register to B inputA Register to A input, B Register to B inputA Register to A input, B Register to B inputA Register to A input, B Register to B inputB Register to Data Bus input, A Register to A inputA Register to Data Bus input, B Register to B inputPIN 3PIN 4PIN 13OUTPUTSELECTIONTRI-STATETM output in high impedance stateTRI-STATE output in high impedance stateTRI-STATE output in high impedance stateTRI-STATE output in high impedance stateTRI-STATE output in high impedance stateTRI-STATE output in high impedance stateTAl-STATE output connected to A RegisterTRI-STATE output connected to B RegisterNote 3: The outpUl control. are sampled bV IN' The TRI·STATE output mu.t be enabled ordi.abledduring the tPlN clock time prior to the roUT clock time at which the output is expected to be true orin the high impedance state. See timing diagram. Two bus~connected devices may be in opposite lowimpedance states simultaneously without damaging either.Note 4: Data Input and Input Control Setup and Hold Times are referenced to the trailing edge oftPIN. whereas the Output Control Timing is referenced to the leading edge of tPIN. See timing diagram.24