Dynamic Shift Registers - Bitsavers - Trailing-Edge

Dynamic Shift RegistersMM4012/MM5012 dual 256-bit dynamic shift registergeneral descriptionThe MM4012/MM5012 dual 256-bit dynamic shiftregister is a monolithic MOS integrated circuitusing P-channel enhancement mode technology toachieve bipolar compatibil ity. The device providesfull read/write control, recirculate logic andan independent wire-OR-able TRI-STATETM outputwhich allows a common output bus-line to beconnected between several registers.The input logic allows recirculating both registersor recirculating either register while loading theother from the data bus input, wh ich along withthe TRI-STATE bus output, is enabled by a 2·input NOR gate wh ich allows multiple addressdecoding. N-bits may be added to the recirculateloop by connecting additional shift registers betweenoutputs A or B and data inputs A or B.features• Bipolar compatibility +5 V, -12V operationNo pull-upor pull-downresistors requ ired• Wide frequency range f min = 400 Hz at 25°Cf max = 2.5 MHz overtemperature guaranteed• TRI-STATE output Common bussystems may bebuilt using wire-ORoutput• System flexibility Chip contains all recir-culate logic, controllogic and shift registerfor disc and drumreplacement memoriesapplications• Disc and drum memory replacement• CRT refresh memory• Serial and parallel data storagelogic and connection diagramsDual-I n-Line PackageOA"!"AINPUTA 1OUTPUT A ZoUTPu~:~~~gi 3OUTPUT ENABLE 4OUTPUT B 515