Dynamic Shift Registers - Bitsavers - Trailing-Edge

Clock Repetition Rate: The range of clock frequenciesfor which register operation is guaranteed.Clock Frequency cJ>t: The range of clock frequencieswhich register operation is guaranteed.Maximum clock frequencies are dependent uponminimum and maximum clock pulsewidth restrictions,as presented by the Guaranteed OperatingCurves.Clock Delay C/>d: C/>d is defined to be that minimumamount of time that must expire after C/>1 hasundergone a V",L to V"'H transition and the startof a C/>2 V",H to V"'L transition. The same spacingsapply, when C/>2 preceeds C/>1 •Clock Phase Delay C/>d, ifid: The time between theVC/>H levels of C/>IN and C/>OUT- C/>d is the time betweenthe trailing edge of C/>IN and the leadingedge of C/>OUT. ~d is the time between the trailingedge of C/>OUT and the leading edge of C/>IN'Clock Pulse Risetime, t,,,,: The time delay betweenthe 1 0% and 90% voltage points on the clock pulseas it traverses between its logic V"'L and logic V",Hlevels.Clock Pulse Falltime, tf",: The time delay betweenthe 1 0% to 90% voltage points on the clock pulseas it traverses between its logic V",H and logic V"'Llevels.Clock Pulse Width, C/>pw: The duration of timethat the clock pulse is greater than 1.5V.Clock Input Levels: The voltage levels (logic V'" Lor V"'H) which the clock driver must assume toinsure proper device operation.Clock Control Setup Time, tcs: The time prior tothe clock Low to High transition at which theclock control must be at its desired logic level.Clock Control Hold Time, tch: The time after theHigh to Low transition for which the clock controlmust be held at its desired logic level.Data Setup Time, tm: The tir;ne prior to the clockHigh to Low transition at which the data inputlevel must be present to guarantee being clockedinto the register by that clock pulse.Data Pulse Width, tdw: The time during;which thedata pu Ise is in its V I H or V I L state.Data Hold Time, ~h: The time after the clockHigh to Low transition which the data input levelmust be held to guarantee being clocked into theregister by that clock pulse.Data Input Voltage Levels: The voltage levels(logic V I L or V I H) which the data input terminalmust assume to insure proper logic inputs.Definition of TermsData Output Voltage Levels: The output voltagelevels (logic Va L or Va H) which the output willassume under normal operating conditions.Data Input Capacitance: The capacitance betweenthe data input terminal and ground referencemeasured at 1 MHz.Output Resistance to Ground: The resistancebetween the output terminal and ground with theoutput in the logic Va H state.Partial Bit Times TIN, TOUT: The time betweenleading edges of clocks, measured at the VC/>Hlevels. TIN is the time between the leading edge ofC/>IN and the leading edge of C/>OUT' TouT is thetime between the leading edge of C/>OUT and theleading edge of C/>IN'Output Sink Current: The current which flowsinto the output terminal of the register when theoutput is a logical low level. Conventional currentflow is assumed.Output Source Current: The current which flowsout of the output terminal of the register when theoutput is a logical High level. Conventional currentflow is assumed.Input Voltage Levels: The logical Low level, VILor VC/>L is the more negative level. This level isgenerally referred to as a TTL or DTL logical "0"and an MOS logical ",". The logical High level,.VIH or V~H is the more positive level. This level isgenerally referred to as a TTL or DTL logical ","and an MOS logical "0".Output Voltage Levels: The logical Low level,VOL, is the more negative level. This is the state inwhich the output is capable of sinking current.The logical High level, VOH , is the more positivelevel. This is the state in which the output iscapable of sourcing current.VGG Current Drain: The average current fl9W outof the V GG terminal of the package with the outputopen circuited.Power Supply Voltage, VGG: The negative powersupply potential required for proper device operation;referenced to Vss.Power Supply Return, VSS: The Vss terminal isthe reference point for the device. It must alwaysbe the most positive potential applied to thedevice.Vss Current Drain: The average current flow intothe Vss terminal of the package. It is equal to thesum of the IGG and 100 currents.Power Supply Voltage, V 00: The negative powersupply potential required for proper device opera·tion, referenced to Vss.cCD....~;::;: _.o~o ....-ICD...3tn279