Dynamic Shift Registers - Bitsavers - Trailing-Edge

MASK PROGRAMMING SPECIALIZESMOS SHIFT REGISTER DESIGNSA quick, economical way of customizing MOSshift register bit lengths is programming the metallizationmask, the mask that defines the thin-filmwiring pattern etched on the silicon wafer- Metallizationetching is the most convenient process stepto specialize because it is consistent from waferto wafer and is the last major process step beforetesting_Utilizing this technique, National Semiconductorhas developed two variable-length dynamic MOSregister designs. Both of them, MM4007/MM5007and MM4019/MM5019, are bipolar compatible.Dual registers 20 to 256 bits long, single registers40 to 512 bits long, and a variety of taps andpinouts provide the system designer with a methodof obtaining custom length shift registers quicklyand at reasonable cost.Up to metal masking, wafer design and fabricationare standardized. No time is lost-or money spentindeveloping custom arrays or tuning up theprocess. Automatic test systems further reduceturnaround time and production costs.Programming the metallization mask mainly involvesrouting signal connections past selectedstorage cells to adjust total register length to thedesired number of cells. Wire-bonding changesprovide output tap options.DUAL REGISTER DESIGNSBasically, each of the variable-length types is adual register (Figure 1 and Table 1A).BriefsSEPTEMBER 1971There are enough storage cells,· I/O stages, clockand power supply lines on each MM4007 chipto make up to two 100-bit registers. The minimumlength of each register half, MA and Me, is 20 bits.The programmable parts, P A and Pe, may be 0 to80 bits long. Lengths need not be equal. Forinstance, register A may be 29 bits and register B76 bits (P A = 9, Pe = 56).v ••VssTOP VIEWFIGURE 1. Dual Shift RegistersAn MM4019/MM5019 chip is similarly organized,except that MA and Me are 40 bits and P A andPe vary from 0 to 216 bits. Again, lengths maybe unequal, such as 240 bits in the A half and 136bits in the B half.Clock and supply line pin locations are standardized,but I/O pinouts are selectable. The I/Oterminals on the chip may be bonded to packagepins which are more convenient for the PC boardlayout. For example, a couple of board feedthroughsmight be eliminated by bonding the Aregister input to Pin 7 (rather than Pin 1) if datacomes in from the right and exits on the left. Or,A and B could share an input pin when they havethe same signal source....CD......a~3:men~......~oCCm33~CCrn'CCD(')mNCDen_.....r+:DCDCCenr+CD...c_.CDenCC~enA. DUAL REGISTERSTABLE 1 ~egister Length OptionsMM4007/MM5007MM4019IMM5019M P TOTAL M P TOTAL(BITS) (BITS) (BITS) (BITS) (BITS) (BITS)A Register 20 Ot080 20 to 100 40 Oto 216 40 to 256B Register 20 Oto 80 20 to 100 40 Oto 216 40 to 256B. SINGLE REGISTERSMA+MB PA +PB MA+MB PA + PB40 o to 160 40 to 200 80 o to 432 80t0512c. TAPPED SINGLE REGISTERSTotal register length same as single registers with tap locations determined by either half of the dual registers.275