Dynamic Shift Registers - Bitsavers - Trailing-Edge

Application NotesOCTOBER 1971»2IU'IU'Ir­o:eLOW FREQUENCY OPERATION WITH DYNAMICSHIFT REGISTERSIn many dynamic shift register applications, it isadvantageous to operate the circuit at low clockfrequencies or in clock burst modes where highfrequency clock rate periods are followed by longintervals in which the clocks are absent. To insurethat his system will operate correctly under theseconditions, the designer should be aware of thelimitations of the type of shift register he is using.There are two basic forms of dynamic shift registercells: the ratioless and the ratio. The ratiolesscircuit of Figure 1a is based on a capacit~r pre·charge concept. During 1>IN clock time, node B isprecharged by transistor 0 3 ; i.e., 0 3 is turned onby 1>IN, creating a low impedance path from nodeB to V GG which charges the node capacitor C 2 toa negative Voltage. Data is coupled at the same timethrough transfer transistor 0 1 to node A, the gateof O 2 , If the incoming data is a positive or "0"level, O 2 will be in a high impedance off state, andnode B will charge to a negative voltage one thresh·old more positive than the 1>IN clock amplitude.When ct>IN returns to a positive level. 0 3 is shutoff, isolating the precharged voltage of node B.The stored charge of node B, coupled with anadditional increment contributed by C 4 , redistributesbetween nodes Band C when the ct>OUTclock turns on transistor 0 4 , The redistributedcharge develops a negative voltage" 1" level acrossC 3 which becomes isolated when 1>OUT returns toa "0" level. The "1" level turns on 0 5 , resultingin a low impedance path between the output of thecell and Vss, establishing a "0" level at the output.In the ratioless cell, there are two nodes whichbecome isolated from any charge replenishingsource during normal operation of the circuit:nodes Band C. These are the nodes which establishthe low frequency limitations of the cell. In mostdesigns node C, the gate of the logic transistor 0 5 ,is the limiting node because total capacitance isless. If we had assumed the initial data coupled by0 1 during ct>IN to be a "1" level, then node Awould of course be the limiting node of the cell.OUTPUTFIGURE la. Ratioless Dynamic Shift Register Cell263