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Dynamic Shift Registers - Bitsavers - Trailing-Edge

Dynamic Shift Registers - Bitsavers - Trailing-Edge

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XMIT KEYRESET XMIT LATCHCHARACTER READYT 0Jl 2341516171891011112113114115116117118191011cMLIJ"'l.-FIGURE 8. ASCII Keyboard I/O Time Slots»zIU'1Nc:(II::s(Q-I::s­(I)mechanical latch on the keyboard. If the keyboardshould lack this facility, an integrated circuit latchcould be added to perform this function.At character read time (T91, the data bus ().II) isgated to an RS flip-flop. For the sake of illustratingthe action sequence, let's assume that a characterready (T9) signal appears on the).ll data bus andthe Xmit latch is set. The data bus line is the datainput to an eight bit shift register. This shiftregister is used to perform the serial to parallelconversion. Nothing further occurs until the nextword cycle is initiated and time slot 1 is reach~d.The Xmit flip-flop has enabled a gate that willgenerate the Xmit key signal at T1 and place thison the).ll bus. This will be received by the KI chipand trigger the transmission of data from the keyboardholding shift register beginning with timeb7~0 b7~1CON. UC LCb6~1 b6~0 b6~0 b6~1TABLE 1. ASCII Keyboard Assignmentsslot 11 and ending with time slot 18 (8 bits long).The Xmit latch will automatically be reset at timeT2. The generation of the Xmit latch will auto·matically be reset at time T2. The generation ofthe Xmit key signal at T1 also causes anotherlatch to be energized (prepare for data). This latchwill enable a gate which at time T11 (the beginningof the data word) will set a clock control latch.This action enables the clock to the output shiftregister for 8 clock pulses. The clock enable latchis reset at time T19. The eight clock pulses to theshift register will permit the entry of the datacoming from the KI ).II bus and accomplish theserial to parallel conversion. At time T19, the dataprep. latch is reset.The character and control codes associated withthe KI device are illustrated in Table 1. The con·0 SP N+l @ \ T4 R6 b7~1~Alpha1 1 S04 A a T2 RO b7~0~Numerics2 " STX B b T3 R43 # ETX C c T3 R2 LC~alpha • b6~ 14 $ EOT 0 d T2 R2 UC~alpha • b6~05 % ENO E e Tl R26 & ACK F f T2 R3 Numbers~Numerics. b6~17 BEL G g T2 R4 Control~Numerics • b6~08 ( BS H h T2 R59 ) HT I i Tl R710.LF J j T2 R611 + VT K k T2 R712 FF L 1 T3 R713 - CR M m T3 R6 • ~Key Legend14 SO N n T3 R5 example15 / Sl 0 0 T4 RO·16 0 OLE P p T4 Rl17 1 DCl 0 q Tl RO18 2 DC2 R r Tl R319 3 DC3 S s T2 Rl20 4 DC4 T t Tl R421 5 NAK U u Tl R622 6 SYN V v T3 R323 7 ETB W w Rl Rl24 8 CAN X x T3 Rl25 9 EM Y y Tl R526 : SUB Z z T3 RO27 ; ESC [ ! T4 R228 < FS \ : T4 R3~29 GS 1 I T4 R4~ ~30 > RS T4 R531 ? US - DEL T4 R7...::s(I)~Q)n(I)::s(I)'< "C­OQ)...Coen...'

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