Dynamic Shift Registers - Bitsavers - Trailing-Edge

»zI01N~~1111111111111I IC:===:=JI GAlA TRANSfER LINE-_"--SIGNALOKCONTAOLLINEfour keyboard interface chips and associated staticswitches in parallel. The device user may specifywhich time slot will be used with a given device.This is especially important when two or more ofthese devices are to be used in a system. If this isleft unspecified in a single keyboard interface chipsystem, this will generally be programmed to theXmit static 1 time slot. It is an illegal conditionfor both a static transmit and key code transmitrequest to occur in the same word cycle.THE KEYBOARD INTERFACEAS USED IN MAPSFIGURE 6. MAPS Block Diagraml 461", :! DM1441The natural environment for this device is tooperate in conjunction with the "timing and control"(T&C) chip (MM5702) of MAPS. MAPS(Microprogrammable Arithmetic Processing System)is a five MOS-LSI chip, mini-processor system.The block diagram shown in Figure 6illustrates the system's primary components andtheir interconnections. Besides the clock lines andpower supplies, the keyboard interface chip has acycle marker (CM) input from the MAPS system.This signal (CM) is generated in the T & Cchip from a master timing clock and is used tosynchronize the entire system including the KI.This procedure is mandatory in a system, such asthis, where all data as well as command and operationsignals are transmitted in a serial by bit andserial by digit basis. The exchange of all informationbetween the system blocks is time multiplexedonto single wire buses; therefore, all of the systemcomponents must be in step. The cycle markerflags the beginning of a 76 bit word cycle time.The important bit times for the KI chip inMAPS are, for example, 11 through 30. Theseare the bit times in any given word cycle thatare allotted for the KI to communicate withthe rest of the system through the T & C chip.The detailed nature of this time period is morecompletely defined and illustrated in Figure 5.The various time slots are logically defined andimplemented within the KI chip as follows: TheCM initiates a delay line composed of a series ofMOS inverters. The outputs of these invertersbecome true in a sequential fashion, one afteranother in step with each clock transition. Therefore,once the sequence is initiated at the propertime (CM) the MOS delay line will behave as aspecial decoded counter in step with the mastercounter in the T & C chip. The output of eachstage will define a precise bit time with respectto the CM. This occurs within the housekeepingblock (Figure 2). When the KI has acknowledgeda key closure it will send out a character readysignal (bit time 20), and continue to send it untilit is acknowledged by the T & C chip. The T & Cchip will receive this and, in some subsequent wordcycle at bit time 12, will send a transmit key,'"Ctil:::sCC...-t::rCD3:3:01.....o~CD< "0"'oQ)...0-:::sr+CD...~Q)(')CD:::sCD< "0"'oQ)...0-m