Dynamic Shift Registers - Bitsavers - Trailing-Edge

nE...CDrn>UJ"C-cao.Q>CD~CCDCJca.......-CDC"C-cao.Q>CD~~o ,....in~~The delay required to avoid switch bounce isaccomplished through the use of the E counter.This counter is incremented each time the Mcounter completes a cycle. The E counter willcontinue to advance until it counts out its programmedmodulus at which time all switch bounceis a thing of the past and the system is allowedto accept the initial key closure as valid. Whenthe first key is released, the E counter is again setto its initial state and allowed to advance to itsterminal state. Upon reaching its terminal state forthe second time, when all switch bounce associatedwith the first key release is over, the reset procedurefor the "1st character" and "busy 1"latches will take place. The modulus of the Ecounter may be varied to accommodate the switchbounce times of the various switches that may beused with this device. This is a parameter specifiedby the customer. The modulus of the E countermay be anything from 1 to 15.If a second key is depressed, while the first keyis held down, a sequence of events very similarto that already described will occur. The basicdifferences are that detection of the second keywill occur as a function of the "any key" signaland the M counter not equal to O. The data readysignal, from the first key closure, must have beenserviced by the system. Otherwise, this is an alarmcondition (two keys depressed simultaneously).After transmission of the first key data and detec·tion of the second key depression, the "2nd character"and "busy 2" latches will be set. The Ecounter will inject its delay and the system willacknowledge and transmit the second character.Should the system be processing two key closuresand receive yet a third, the alarm latch will gotrue. The third key depression is detected whenthe "any key", M =1= 0", and "second character" inprocess" signals occur simultaneously. When thealarm latch goes true, a signal may be transmittedto the rest of the system on the data bus. Thealarm latch is reset through the use of the clearkey or by a reset pulse on the data bus.The remainder of the housekeeping logic acceptsthe input signals from the data bus and transmitsdata out on the bus at the proper time. The timedsequence for the data bus associated with thisdevice is shown in Figure 5. We have alreadydiscussed the nature of the keyboard alarm, characterready, and Xmit key signals. The alarm setand reset signals are inputs from the rest of thesystem that cause or remove the alarm condition.The test input is for testing purposes only. It isused to speed up the testing of this device whenthe inputs to the device are generated from controlled(bounce free) sources. Therefore there isno need for the normal system delays. The systemcould conceivably be used by the O.E.M. manufacturerfor incoming receiving inspection, just asthe factory uses it. A more exact understanding ofits use should be acquired from the factory beforeit is used.The static Xmit inputs are used to cause the keyboardinterface to deliver the data stored in thestatic switch holding register at the immediatenext appropriate time. There are four of thesestatic Xmit input pulses to permit use of up toNinI2:«XMIT KEYSHIFT CODESTATIC XMIT 1STATIC XMIT 2STATIC XMIT3STATIC XMIT 4ALARM SETALARM RESETCHARACTER READYKEYBOARD ALARMJL~OIAhIAIhlohlcLFIGURE 5. MM5704 1/0 Time Slots256