Dynamic Shift Registers - Bitsavers - Trailing-Edge

condition is specified (Pin 2 = V GG ). If lower caseis specified (Pin 2 = Vss) the output wi.1I be generatedby the lower 32, 9-bit words. The outputfrom the ROM is loaded in parallel into a 9-bitshift register (Key Register) upon command fromthe housekeeping logic. This command is generatedafter the housekeeping logic has acknowledged agenuine key closure. A "Character Ready" signalis also sent out via the data bus to the rest of thesystem, at the same time. Upon receipt of thetransmit signal (Xmit key) the key register willtransmit its information out on the data bus ina bit serial manner, at the proper time. Thecontents of the ROM contain character codes thatare completely specified by the customer. Thereforethis device becomes in effect part of hiscustomized system.The static switches are interrogated by the scanlogic and entered into the static switch holdingregister at T5 time with each scan cycle. Thesesignals bypass the ROM and are switched directlyfrom the static switch holding register onto thedata bus serial fashion upon command from thesystem.The housekeeping logic performs many tlmmgand control functions which are initiated upondetection of a key closure or an input from thedata bus. These are listed below:1. Provides for elimination of switch bounce. (Forboth conditions-when the key is depressed andreleased). This feature is adjustable to accommodatethe different switch bounce times thatexist with different keyboard switches.2. Provides two key rollover.(a) Detects first key closure and generates"Busy 1"(b) Detects second key closure and generates"Busy 2"3. Provides three key alarm.4. Provides the signals ("Alarm" and "CharacterReady") to the data bus at the proper time.5. Accepts input commands (Xmit key, Alarm. Reset, etc.) from the data bus and processesthem. (See Figure 5.)The housekeeping logic performs most of its functionsupon initiation from any key signal. Thissignal is generated by detecting when any of the Rlines are true. Two key rollover detection is accomplishedthrough the use of a counter (M counter)whose modulus is equal to the keyboard scancounter (33). The sequence of events is as follows:The initial key closure is detected and the "AnyKey" signal is generated, which performs the followingfunctions: It sets a flip-flop which generatesthe "Busy 1" signal. It initializes the M andthe E counters (the E counter will be dealt withlater). It sets. another latch (1st character FF)which prevents any additional "Any Key" signalsfrom affecting the state of M .and E counters andthe "Busy 1" latch. The M counter is now timelocked to the first detected "Any Key" signal.The signal that delays the B counter in the scanlogic also delays the M counter. This enables theM counter to remain time locked to the scancounters and permits multiple key depressions tobe detected. The first key time slot will always becoincidental with the M counter equal to 0 time.Any other key depression will generate the "AnyKey" signal at the time when the M counterdoesn't equal O. This is more clearly illustrated inFigure 4.For purposes of illustration it is assumed that keyclosure was detected at scan counter time 18. The"1 st character" and "busy 1" latches will remainin the true state until the system has delayed longenough to eliminate switch bounce (key closure)and acknowledges the receipt of the valid character.This action switches the contents of the ROMinto its output shift register, and sends out a "dataready" signal on the data bus. The "1st character"and "busy 1" latches go false when the release ofthe first key is detected, again with sufficientdelay to eliminate switch bounce (key release).»zI(J1NCen::l