Dynamic Shift Registers - Bitsavers - Trailing-Edge

enECD....en>tJ)"C...~o.c>CD~c:CDCJ~'t:CD....c:Nit)IZc:(TO BLOCKM COUNTERThe Scan.. Logic will sequentially interrogate eachkey of the keyboard. It provides the timed interrogationpulses. The detection of a key closure isaccomplished by the ROM input control logic.This results due to the Rand B line being com-·bined in an AND condition at the input to theROM control logic. The rate at which the keyboardis scanned is basically determined by theclock input. Provision has been made internal tothis logic block to compensate for the variouscapacitive loads that different keyboards mightpresent. This is a programmed feature. The scanlogic is shown in greater detail in Figure 3. It isdesigned to sequentially scan 32 keyboard switchesin a 4 x B matrix as shown in Figure 2. The T linesenable each of the four quadrants in sequentialfashion. The B lines are then used to sequentiallydecode the B R lines at the ROM input. As theA counter changes from state N to N+1 a pro·grammable delay times out before the B counteris allowed to decode the R lines within the quad·rant. This delay is necessary to allow the T line tocharge the capacitance, associated with that quadrantof the keyboard switch matrix, to its fullvalue, and discharge the capacitance associatedwith the last quadrant to be scanned.The delay is accomplished through the use of theD counter in the following fashion: The samesignal from the B counter output that advancesthe A counter sets a latch (block flip·flop) whichin turn inhibits any further advancement of theB counter. It also sets the D counter to an initialstate from which it must advance until a signal isgenerated in its output which resets the blockflip·flop. This enables the B counter to advancethrough its cycle until its terminal state is reachedand the A counter is again advanced, at which timethe cycle is reinitiated. The degree of delay that isgenerated by the D counter is a function of theclock input to the counter and the modulus of thecounter. The modulus of the D counter may be.specified by the customer to be any value from1 to 15. Either the {} in clock or the cycle marker(CM) from the system may be used to advancethe D counter. Since both of the signals are generatedand controlled external to the device, thedelay resulting from this technique is completelyFIGURE 3. Scan Logic of MM5704adjustable over a reasonably broad range. Thisdelay must exceed that time required by the systemto fully charge or discharge any keyboardcapacitance associated with any given T line. T4duration will always be equal to and may be greaterthan the duration of the other T lines.The following example will serve to clarify theuse of the D counter to develop a programmeddelay for a given keyboard capacitance. Assume akeyboard capacitance of 300 pF and a clock ({})rate of 500 kHz with a pulse width of 500 ns.Also, we are given a .5 mA current source tocharge the T /R line capacitance with each 500 nsclock pulse width. Using the math function:WhereV =i . tV =­cV = the voltage developed across thecapacitori = the charging currentt = the charging timec = the capacitance(15 x 10-3 ) (500 x 10-9 )(.3 x 10.9 )= .B3VWe know that a voltage of BV is a safe MaS "1"level voltage, and if our capacitance charges .B3Vwith each clock pulse then we will need approxi·mately 10 clock cycles to charge the T linecapacitance of BV or greater.10 x .B3V = B.3VTherefore, the modulus of the D counter should bespecified at 10 and it should be driven from theclock ({}) to meet the requirements of this particularkeyboard.The ROM accepts detection of any given keyclosure along with the "Case" signal input andproduces a 9-bit parallel output. The ROM outputis serialized and transmitted on the data bus at theproper time and upon command to the rest ofthe system. The output of the ROM will be takenfrom the upper 32, 9·bit words if the upper case254