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Dynamic Shift Registers - Bitsavers - Trailing-Edge

Dynamic Shift Registers - Bitsavers - Trailing-Edge

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signal is generated at the alarm output (pin 1) andan alarm pulse may be transmitted .to the rest ofthe system via the data bus. The ability to signalthe alarm condition on the data bus is a programmablefeature. The signal made available atPin 1 may be used to inform the operator of theexistence of the alarm condition. The alarm conditionwill also be triggered if two or more keysare depressed simultaneously, such that the secondkey closure is detected before the first key closurecan be processed and transmitted.IDLE KEY RESET (PIN 9)An automatic reset signal is generated during theidle key mode of operation. This mode is definedas no keys depressed and power is on. The resetsignal is created by charging an external capacitor(CR) which enables the control logic to detectfirst key closure. The purpose of the reset is toprevent keyboard lock-up due to mass depressionof the keys, or any other attempt to void theintegrity of the keyboard interface chip. An exampleof this might be, depressing three or morekeys (including the clear key) to force an alarmcondition to repeat thereby voiding the keyboardlogic. When such an attempt occurs, as soon as thekeys are released and the bounce delaY'is timedout, the idle key reset enables the control logic.KEYBOARD MATRIX~,--SC_ANLOG,--I' f (~ -- ~,~."~ -~ltlIILff.-L1 LffLJ 4f1J IL _____ _The value of the reset capacitor (CR) is dependenton the keyboard scan cycle.'i . tCRV,Where: average charging current = 1 mAV1 reset voltage ~ 3.0Vt charging time intervaltE+nTWhere: E modu 10 of E cou ntern = number of scan cycles beyondbounce out delay = 2(Jf = frequency of clock (Jin.Typical values for CR, that would fit most applications,range from 0.001 J.l.F to 0.1 J.l.F.HOW IT WORKSAs may be seen by the simplified block diagram inFigure 2, the keyboard interface chip is partitionedinto three basic logic areas. These areas are theScan Logic, the ROM encoder (with its associatedinput control logic and output data converter), andthe system housekeeping logic.:______ JRLiNES.usu»2IUIN_.:lCD< "C'om..Q.CJ)

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