Dynamic Shift Registers - Bitsavers - Trailing-Edge

enCo....ca...CI):EencoUECI)....en>enenCI)'':oECI):?!enenCI)C.JC.J«Eo"'CCcaa:eno:?!C.JEcac>C1 00 ns might result in some system designs. Thiseasily offsets the access specification of 350 ns inthe MM5260. This included an output delay ofsome 40 to 50 ns in the MM5260 access andcycle times because of on chip output TTL compatiblebuffering. This delay in the TRI-STATEsense amplifier in the MOS chip was considereda worthwhile tradeoff to achieve the benefitsalready cited for the common TRI-STATE I/Otechnique.It might be noted that the TRI-STATE TTL busbuffers will drive long buses at high speed withhigh noise immunity. Therefore, the common I/Obus can extend well into the system structure.SYSTEM COST SAVINGSThe obvious savings in system costs are listed inTable 2. These consist of 17 interface and controlcircuits, 8 dual sense amplifiers, 14 resistors, anda need for only two supplies (+5, and -12) insteadof high-level supplies of (+20, +16, +5 and -5). Onecan also add proportional savings in printed-circuitboard costs, cooling hardware, assembly, componenttest, inventory control, and so forth.Effective packing density is higher, because theMM5260 has two less pins than the 1103 (obtainedby common I/O), one less supply, and less stringentcooling requirements. More RAM circuits can bepacked into the same volume; more also can beadded on bigger boards when system designerswant to increase word length or module wordcapacity. Smaller boards, of course, further reducesystem packaging costs.CONCLUSIONSSavings using the MM5260 in a typical memorysystem module are 66% less pOl/\.er dissipation,50% fewer overhead circuits, and 66% less, overheadcost. Speed performance is not curtailed and,in many applications, an improvement may beachieved.These advantages stem from a combination ofthree techniques: TRI-STATE common I/Ostructurewith an internal sense amplifier, precharge decoding,and bipolar compatibility. All are orientedtoward system advantages, rather than cost/speedimprovements at the device level.4K x 16 Memury ModuleusingMM5260oI.!')IZ«1 K Dyn.mic MOS RAMFIGURE 7. 1103-Type and MM5260 Modules. The 1103 memory module utilizes NH0026level translators in place of 36 DM74451 and NH0027 elements.250