Dynamic Shift Registers - Bitsavers - Trailing-Edge

submodule is selected at a time by two bits of theDM7442 TTL decoder address. The same decodercould access eight submodules with a 3-bit address,and so forth. This is standard decoding practice.The external data selectors (DM8123) and read/write bus buffers (DM8093 and DM8094) areTR I-STATE TTL devices. 1 These have high-speed,active-pullup outputs when enabled. The two typesof buffers can operate in parallel with the internalMOS input/output mode read/write gates. Onecontrol line gates both in complementary fashionbecause one is enabled by an "0" and the other bya "1". The data selectors hold off accesses duringa submodule's refresh intervals. Figure 3 is theTTL clock forming and timing control circuit forthe module.FIGURE 3. System Clock Timing and Control CircuitPRECHARGE DECODINGDuring standby, each MOS RAM circuit dissipatesabout 75 mW. To achieve memory access, apulse called the "precharge" is applied to set upthe decoders and other I/O functions. Prechargeminimizes system power dissipation by making itunnecessary to energize decoding logic betweenselects. During a 600 ns access, MM5260 powerdissipation goes up to 400 mW.It is important to keep as many as possible of theRAM circuits on standby to minimize systemaverage power dissipation. Excessive dissipation,without adequate cooling in a high-density system,would overheat the semiconductor junctions. Theonly ways of preventing overheating, should averagedissipation be high, are to slow down speed andlose performance, reduce packing density, or increasesystem cooling hardware. Average powersupply and clock-driving requirements are alsoreduced by precharge modulation or by reducingthe rate of precharge pulse. The added circuitryto effect power minimumization is only threeelements.Figures 2, 3 and 5 illustrate the most effective wayyet developed to decrease precharge power dissipation.This "precharge decoding" method appliesprecharge to a submodule only when that moduleDon Femling, "TRI-STATE Logic in Modular SystemOrganizations," National Semiconductor AN-43, April1971.is selected. This is implemented by having thechip-enable of the decoder gate the precharge clockvia the TR I-STATE TTL data selectors in theclock circuitry. Simultaneously, the I/O directionsare controlled. Selective precharge decoding canyield an ultimate average power dissipation of77 mW.MEMORY TIMINGThe MM5260 timing control is quite simple becauseof precharge decoding and the I/O structure.As indicated in Table 1, maximum cycle time is600 ns. A delay of 100 ns before precharge isallowed for address settling and decoder operation.This allowable delay will not affect the access timeunder worst case conditions. This element designcharacteristic permits a very straightforward selectiveprecharge decoding technique which does notaffect the performance of the memory system.Precharge goes low for 250 ns to set up thedecoders, then returns to conserve power.'""""=i x='""~ r-UABlE I lAC \ /"''"'"''~''--r-'-~O~TA""'DATAINPUTFIGURE 4. MM5260 Timing DiagramIf read is commanded, the read gates are enabledand the write gates disabled at the outputs. Storeddata is available at the output within 350 ns of thestart of the access. Write may be commanded justprior to the precharge trailing transition and iscompleted by the end of the 600 ns cycle.Address, precharge, and chip select timing is notcritical. A skew of about 50 ns between addresstiming by the CPU and leading and trailing edges ofchip-select and precharge will not affect accesstime, cycle time, or overall memory speed.DEVICE COMPARISONSThe 1103-type MOS RAM comes closest of previousMOS RAM designs to the MM5260 in performanceand organization. It is also a 1024-bitdevice with chip select and on-chip decoding of10-bit word addresses. The package has two additionalpins, one for the extra power supply andanother because data outputs and inputs areseparate.»zI(J1oc