Dynamic Shift Registers - Bitsavers - Trailing-Edge

DYNAMIC MOS RANDOM ACCESSMEMORIES SYSTEM CONSIDERATIONSABSTRACTA new TRI-STATETM common I/O configuration,capable of precharge decoding without losing systemperformance and bipolar compatibility, isemployed in a 1024-bit MOS RAM. In combination,the techniques reduce typical memory modulepower dissipation some 66%, number of overheadcircuits by 50%, and overhead costs by 66%without sacrificing system speed. Performance andcost of the new RAM are compared with those ofan earlier design in a similar system application.INTRODUCTIONUnlike earlier advances in MOS memories, theadvantages offered by the MM5260 MOS RAMdo not stem from a new process. I nstead, a newcombination of operating techniques is used tosolve system cost/performance problems. The techniquesare a TR I-STATE I/O structure at a commonI/O terminal, precharge decoding, and bipolarcompatibility.Memory size, cost and propagation delay of themonolithic MOS random-access device were notdecreased. These savings could have been realizedquite easily at the device level by foregoing someof the system advantages. The result at the systemlevel though is very low average power dissipation,simplified timing control, fewer and fasterinterface devices with the external system, reducedcooling requirements; elimination of high-levelApplication NotesAUGUST 1971MOS supplies, and other cost reductions. Chiefly,dissipation is reduced by 66%, overhead circuitsby 50%, and overhead cost by 66% with no lossof speed.To make these points realistic, the new design willbe compared, in a system environment, with anotherMOS RAM design with slightly faster accessand cycle times specified at the device level.MOS STORAGE DEVICEThe internal design of the new MM5260 (Figurela) is fairly standard except for its bipolarcompatibility, I/O structure, and precharge decoding.The 1024 storage cells are in a 32 x 32 array_ A10-bit address is X-V decoded on the chip toaccess a cell. In each cell, 0 1 is the storage element,O 2 a read gate, and 0 3 a write gate. An MOS "1"is stored by charging the capacitance of 0 1 and an"0" by not charging it. Read consists of sensingthe data level after an access is made.Bipolar compatibility means that all data andaddress inputs sense bipolar data levels and thatdata .is read out at the original data leVels. Thiseliminates external level translators at inputs andsense amplifiers at outputs. Previous MOS designsrequired these interface circuits in a typical memorymodule. The common I/O terminal on theMM5260 is made possible by the I/O structurel>2Ic.noc