Dynamic Shift Registers - Bitsavers - Trailing-Edge

output of the last register are connected as inFigure 1, and the registers in between are simplydaisy-chained by connecting each serial output tothe next serial input. All seven rows would use140 register packages.The character data for this type of system can beformatted by a standard character generator. Forinstance, the standard ASCII code can address abipolar compatible read-only memory such asNational's MM5241AA, which is programmed togenerate 5X7 dot-type characters for CRT display.However, in the lamp display system, the displayrefresh function is handled without an additionalmemory. The column bits are entered in eachregister chain, as before, through the input gatingat a rate determined by the clock rate suppliedthe MH0025C clock driver. The MH0025C is atwo-phase driver. However, since the MM5081takes a single-phase clock input (converted to atwo-phase clock inside the register package), onlyone of the dual drivers in the MH0025C packageis shown (the other half can be used to share theclock-drive load).After the registers are loaded, the clock into thedriver is dropped to a frequency of 2 Hz, if theregister was loaded at a higher frequency. This rateis stabilized by the coupling capacitor Ce. Thecoupling capacitor on this type of driver determinesthe maximum pulse width, but the minimumpulse width is established by the clocksignal. So, at the lower frequency, the characterssweep smoothly from right to left across the displaylamps. They repeat the message every 100seconds because 200 register stages are in each ofthe seven parallel rows.Both the clock driver and the registers operate offthe 10V and -6V power supplied.1 5DHz 1... --, r--1 r---125 L..J L.JON OffNEW DATAINPUTswitch. The purpose is to limit the current andvoltage across the lamps and the MaS output transistorsto ensure that they operate reliably andhave long lives. Also, the method reduces powerconsumption and allows lower power, inexpensivehigh-voltage power supplies to be used.The high-voltage switch seen in Figure 3 anddetailed in Figure 4 switches at a rate of 50 Hz anda duty cycle of 25%. Thus, when any of the MaSoutput transistors is on, the lamp that is "on"during that 250 msec display-rate interval (1 00%duty cycle at 2 Hz) is actually on for only 5 msecat a time. Then it turns off for 15 msec. This refreshrate was chosen because it provides a goodlamp intensity with no apparent flicker.-.. "6'L--'\"""_ ....._ .....()_12••FIGURE 4. High Voltage SwitchThe -125V supply turns on the lamps, and the-45V supply turns them off. But what is actuallybeing used is the voltage difference, or bias. Mostglow-discharge lamps require a 65V starting voltageand a 60V holding voltage. The switch keeps thelamps alternating between these levels while theMaS transistors are on, but imposes a maximumvoltage of only -65V on the MaS transistors (thatis, 125-60V) for the 5 msec "on" time. TheMM5081 can easily take this - the spec allows-100V at 60 Hz (or 16.66 msec) and they arestress-tested to this level.INDUSTRIAL DISPLAYS3:o