Dynamic Shift Registers - Bitsavers - Trailing-Edge

Dynamic Shift RegistersMM4001A/MM5001A dual 64-bit dynamic shift registerMM4010A/MM5010A dual 64-bit accumulatorgeneral descriptionThe MM4001A/MM5001A dual 64-bit dynamicshift register is a monolithic MOS integrated circuitutilizing P-channel enhancement mode lowthreshold technology. The device consists of two64-bit registers with independent two phase clocksand is guaranteed to operate at a 2.5 MHz operatingfrequency for CRT display appl ications.The MM401 OA/MM501 OA is a dual accumulatorfunction capable of operating at very high frequency.The device is also constructed on a singlesilicon chip utilizing MOS P-channel enhancementtransistors. With the recirculate control line at anMOS logic "0" state, the device functions as anaccumulator. A logic "1" state at the recirculatecontrol line allows external information to enterthe register serially. It is important to note thatrecirculation of data is performed internally, independentof the output circuit thus making itinsensitive to output loading.features• High frequency operation 3.3 MHz typ• Low power consumption 0.4 mW/bit at 1 MHz• DTLlTTL compatibility +5V, -12V powersupplies, push-pulloutput stage• Minimum operating frequency guaranteed250 Hz at 25°C• Application versatility "Split clock" opera-tion, independentcontrol of eachregister forMM4001 A/MM5001 Aapplications• Business machine• CRT refresh memory• Delay line memory• Arithmetic operations3:3:~o-l>.......3:3:C1Io-l>3:3:~o-ol>.......3:3:C1Io-ol>connection diagramsload control truth tableMM4001A1MM5001AMM4010AlMM5010AMM4010A/MM5010ALOGICAL HIGH LEVEL(VLCH )Recirculates "old" dataLOGICAL LOW LEVEL(VLcdLoads" new" dataNola: Pin 5 ~onllll£tedto~lI$Ii.TOPI,fIEWNote: Pin 5 connected IDcase.TOP VIEWtypical applicationsMM4001A/MM5001A TTL/MOS InterfaceMM4010A/MM5010A TTL/MOS InterfaceI MM4010A/MM5010AL.:---------v-;;;,r' ..-1211 9)N \'>oUT15